• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.5
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• pp.892-897
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• 2007

This paper presents the output filter design and the output characteristic analysis by cut-off frequency set up of the LCR filter on NPC multi-level inverter with trap-filter. The single-phase NPC three-level inverter operates at low switching frequency. The proposed LC trap filter is comprised of a conventional LCR output filter, by using LC trap filter the need for high damping resistor and low LC cut-off frequency is eliminated. Also. low damping resistor is increased the output filter system. The multilevel inverter system used NPC type inverter in proper system for high power application and controller is used DSP(TMS320C31). The effectiveness of proposed system confirmed the validity through SPICE simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2168-2180
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• 2014

In this paper, a generalized power loss algorithm for multilevel neutral-point clamped (NPC) PWM inverters is presented, which is applicable to any level number of multilevel inverters. In the case of three-level inverters, the conduction loss depends on the MI (modulation index) and the PF (power factor), and the switching loss depends on a switching frequency, turn-on and turn-off energy. However, in the higher level of inverters than the three-level, the loss of semiconductor devices cannot be analyzed by conventional methods. The modulation depth should be considered in addition, to find the different conducting devices depending on the MI. In a case study, the power loss analysis for the three- and five-level NPC inverters has been performed with the proposed algorithm. The validity of the proposed algorithm is verified by simulation for the three-and five-level NPC inverters and experiment for three-level NPC inverter.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.8
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• pp.430-435
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• 2006

This paper presents a method about the efficiency analysis and the harmonic reduction of single phase NPC multi-level inverter with LC-trap filter and LCR output filter. The proposed LC-trap filter is comprised of a conventional LC output filter, by using LC-trap filter the need for high damping resistor and low LC cut-off frequency is eliminated. Also, low damping resistor is increased the efficiency of the output filter. Experimental verification of the proposed circuit is provided with single phase NPC multilevel inverter system and DSP controller.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.4
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• pp.313-320
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• 2006

In this paper, a design approach of LC trap filter for output side harmonic reduction of single phase NPC multilevel inverter is proposed, and THD of the output voltage and harmonic FFT of the output current are analyzed. The proposed filter consists of a conventional LCR filter cascaded with an LC trap filter and it is tuned to inverter switching frequency. A NPC multilevel inverter inverter is used an inverter system for high power application and DSP(TMS320C31) is used for the controller. The effectiveness of the proposed system confirmed through simulation and experimental results.

• Journal of Power Electronics
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• v.19 no.3
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• pp.702-713
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• 2019

Multilevel Inverters (MLIs) are widely used in medium voltage applications due to their various advantages. In addition, there are numerous types of MLIs for such applications. However, the diode-less 3-level (3L) T-type Neutral Point Clamped (NPC) MLI is the most advantageous due to its low conduction losses and high potential efficiency. The power circuit of a 3L T-type NPC is derived by the conventional two level inverter by a slight modification. In order to explore the MLI performance for various Pulse Width Modulation (PWM) schemes, this paper examines the operation of a 3L (five level line to line) T-type NPC MLI for various types of Multi-Carriers Pulse Width Modulation (MCPWM) schemes. These PWM schemes are compared in terms of their voltage profile, total harmonic distortion (THD) and conduction losses. In addition, a 3L T-type NPC MLI is also compared with the conventional NPC in terms of number of switches, clamping diodes, main diodes and capacitors. Moreover, the capacitor-balancing problem is also investigated using the Neutral Point Fluctuation (NPF) method with all of the MCPWM schemes. A 1kW 3L T-type NPC MLI is simulated in MATLAB/Simulink and implemented experimentally and its performance is tested with a 1HP induction motor. The results indicate that the 3L T-type NPC MLI has better performance than conventional NPC MLIs.

• Journal of the Korean Society for Railway
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• v.15 no.2
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• pp.129-134
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• 2012

In this paper, speed control of IPMSM drives for the next generation domestic high speed railway system using NPC 3-level inverters is presented. The NPC multilevel inverter is suitable for the high-voltage and high-power motor drive system because it has advantages in that the voltage rating of the power semiconductor devices and output current harmonics are reduced. For the speed control of IPMSM using NPC 3-level inverters, maximum torque control is applied in the constant torque region, and filed weakening control is applied in the constant power region. Simulation programs based on MATLAB/Simulink are developed. Finally the designed system is verified and their characteristics are analyzed by the simulation results.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.4
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• pp.333-342
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• 2009

Three-level Diode Clamped Multilevel Inverter, generally known as Neutral-Point-Clamped (NPC) Inverter, has an inherent problem causing Neutral Point (NP) potential variation. Until now, in many literatures NP potential problem has been investigated and lots of solutions have also been proposed. However, under fault and fault tolerant control, distinctive feature for NP potential variation problem was rarely published from the standpoint of reliability. In this paper, NP potential is analytically investigated both normal and faulty conditions under carrier based PWM. Subsequently, relation between fault detection time and size of capacitor is analyzed. This information is explored by simulation and experiment results, which contribute to enhance the reliability of inverter system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.2
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• pp.324-330
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• 2015

Energy Saving Methods in existing railway vehicle are considered by active approach such as regenerative energy storage and utilization, eco driving, etc. On the other hands, energy saving measures in railway station are operated by passive method such as reduction of operating time in ventilation system, cooing system and power equipment. To reduce energy and for independence in railway system, it requires an active energy saving measures. It needs to its own power source besides the power source of electric supply company such as renewable energy and regenerative energy and take the advantage of power storage system and stored power are used in optimum time. This paper deal with 3-level NPC inverter and T-type NPC inverter that used in various multi-level topology applicable to the railway system.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.385-387
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• 2008

Three-level Diode Clamped Multilevel Inverter, generally known as Neutral-Point-Clamped(NPC) inverter, has an inherent problem causing Neutral Point(NP) potential variation. Until now, in many literatures NP potential problem has been investigated and lots of solutions have also been proposed. However, in the case of NP potential variation was rarely published from the standpoint of reliability. In this paper, NP potential is analytically investigated both normal and fault conditions under carrier based PWM. Subsequently, relation between fault detection time and size of capacitor is analyzed. This information is explored by simulation results, which contribute to enhance the reliability of the NPC inverter system.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.2
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• pp.135-141
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• 2006

In this paper, LC output filters are designed to reduce output harmonics and harmonic analysis are peformed. Generally, multilevel inverters are used in high power application and operates with low switching frequency, which, in turn, generates large output harmonics. Output filters we used to reduce output harmonics. The design approach to reduce output harmonics of the 31eve1 multilevel inverter is discussed and DSP(TMS320C31) is used for the digital control of the system. The design example is given. The designed system is verified by simulation and experiment.