• Proceedings of the Korean Operations and Management Science Society Conference
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• 1996.10a
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• pp.225-228
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• 1996

This paper proposes a design methodology for distributed databases connected by a LAN. Two primary objectives of the methodology are (i) to allocate data files and workload among heterogeneous servers and (ii) to determine the number of servers to satisfy the response time required for processing each transaction. The file and workload allocation decision is formulated as a nonlinear zero-one integer programming problem. This problem is proven to be NP-complete. A heuristic is developed to solve this problem effectively. A decision support system is implemented and an example is solved to illustrate the practical usefulness of the system.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2006.05a
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• pp.1124-1132
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• 2006

This paper considers a flow shop scheduling problem where a different WIP (work-in-process) state has different weight on the duration time. The objective is to minimize the sum of the weighted WIP. For the two machine flow shop case, the recognition version is unary NP-Complete. The three simple and intuitive heuristics H0, H1, and H2 are presented for the problem. For each heuristic, we find an upper bound on relative error which is tight in limit. For heuristic H2, we show that H2 dominates the other two heuristics.

• Journal of applied mathematics & informatics
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• v.5 no.2
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• pp.329-336
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• 1998

The class of doubly chordal graphs is a subclass of chordal graphs and a superclass of strongly chordal graphs which arise in so many application areas. Many optimization problems like domination and Steiner tree are NP-complete on chordal graps but can be solved in polynomial time on doubly chordal graphs. The central to designing efficient algorithms for doulby chordal graphs is the concept of (canonical)doubly perfect elimination orderings. We present linear time algorithms to compute a (canonical) double perfect elimination ordering of a doubly chordal graph.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.6
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• pp.514-523
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• 2002

Feeder arrangement is an important element of process planning for printed circuit board assembly systems. This paper newly proposes a feeder arrangement method for multihead-gantry chip mounters. The multihead-gantry chip mounters are very popular in printed circuit board assembly system, but the research has been mainly focused on single-head-gantry chip mounters. We present an integer programming formulation for optimization problem of multihead-gantry chip mounters, and propose a heuristic method to solve the large NP-complete problem in reasonable time. Dynamic programming method is then applied to feeder arrangement optimization to reduce the overall assembly time. Comparative simulation results are finally presented to verify the usefulness of the proposed method.

• 제어로봇시스템학회:학술대회논문집
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• 1990.10b
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• pp.1250-1255
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• 1990

This paper discusses an optimal cyclic scheduling problem for a FMC (Flexible Manufacturing Cell) modeled by a two-machine flowshop with two machining centers with APC's (Automated Pallet Changers), an AGV (Automated Guided Vehicle) and loading and unloading stations. Cyclic production in which similar patterns of production is repeated can significantly reduce the production lead-time and WIP (Work-In-Process) in such flexible, automated system. Thus we want to find an optimal cyclic schedule that minimizes the cycle time in each cycle. However, the existence of APC's as buffer storage for WIP makes the problem intractable (i.e., NP-complete). We propose an practical approximation algorithm that minimizes, instead of each cycle time, its upper bound. Performances of this algorithm are validated by the way of computer simulations.

• Proceedings of the Korean Society of Computer Information Conference
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• 2011.01a
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• pp.289-292
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• 2011

본 논문에서는 유전 알고리즘을 이용한 강의시간표 작성 시스템 설계 방법을 제안한다. 강의시간표는 교과목의 강의시간, 강의실, 교수자 등의 정보를 시간표 테이블에 할당하는 문제이면서 스케줄링 문제이다. 강의시간표로써의 의미를 가지기 위해서는 강의실 중복 회피, 교수의 강의시간 중복회피와 같은 필수 제약조건(Hard Constraint)을 만족해야 한다. 또한, 강의시간표 문제는 NP-Complete 문제로 알려져 있으며 기존의 Exact 알고리즘으로는 최적 해를 구하는 것이 힘들다. 따라서 본 논문에서는 휴리스틱 알고리즘 중의 하나인 유전 알고리즘을 교과목의 강의시간 배정 부분과 강의실 배정 부분을 각각 별도의 부시스템 (Sub-system)으로 나누어 적용하는 방법을 제안한다. 실험 결과 강의시간표로써의 의미를 가질 수 있는 필수 제약 조건을 만족시킬 수 있음을 알 수 있었다.

• ETRI Journal
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• v.20 no.4
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• pp.327-345
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• 1998

This paper deals with the problem of one-to-one mapping of 2$^n$ task modules of a parallel program to an n-dimensional hypercube multicomputer so as to minimize the total communication cost during the execution of the task. The problem of finding an optimal mapping has been proven to be NP-complete. First we show that the mapping problem in a hypercube multicomputer can be transformed into the problem of finding a set of maximum cutsets on a given task graph using a graph modification technique. Then we propose a repeated mapping scheme, using an existing graph bipartitioning algorithm, for the effective mapping of task modules onto the processors of a hypercube multicomputer. The repeated mapping scheme is shown to be highly effective on a number of test task graphs; it increasingly outperforms the greedy and recursive mapping algorithms as the number of processors increases. Our repeated mapping scheme is shown to be very effective for regular graphs, such as hypercube-isomorphic or 'almost' isomorphic graphs and meshes; it finds optimal mappings on almost all the regular task graphs considered.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.23 no.59
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• pp.1-10
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• 2000

The traveling salesman problem is a representative NP-Complete problem. It needs lots of time to get a solution as the number of city increase. So, we need an efficient heuristic algorithm that gets good solution in a short time. Almost edges that participate in optimal path have somewhat low value cost. This paper discusses the property of nearest neighbor and 3-opt. This paper uses nearest neighbor's property to select candidate edge. Candidate edge is a set of edge that has high probability to improve cycle path. We insert edge that is one of candidate edge into intial cycle path. As two cities are connected. It does not satisfy hamiltonian cycle's rule that every city must be visited and departed only one time. This paper uses 3-opt's method to sustain hamiltonian cycle while inserting edge into cycle path. This paper presents a highly efficient heuristic algorithm verified by numerous experiments.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.5
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• pp.976-998
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• 2011

This paper attempts to maximize the operator's revenue while simultaneously providing a multi-constraint, multi-hop and deterministic QoS provisioning for real time traffic in IEEE 802.16m based 4G networks. The optimal solution to such a problem is NP-complete and therefore not feasible to be solved in a tolerable polynomial time. For this reason, we also provide a simple price based greedy heuristic to be used along with the admission control. Simulation results for different QoS schemes show that the heuristic produces a revenue that is very close to the optimal revenue, and is far more aggressive than the size based and other common algorithms that are computationally feasible to be implemented in IEEE 802.16m.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.71-79
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• 1993

This paper proposes a new test pattern generation methodology for combinational logic circuits using neural networks based on a modular structure. The CUT (Circuit Under Test) is described in our gate level hardware description language. By conferring neural database, the CUT is compiled to an ATPG (Automatic Test Pattern Generation) neural network. Each logic gate in CUT is represented as a discrete Hopfield network. Such a neual network is called a gate module in this paper. All the gate modules for a CUT form an ATPG neural network by connecting each module through message passing paths by which the states of modules are transferred to their adjacent modules. A fault is injected by setting the activation values of some neurons at given values and by invalidating connections between some gate modules. A test pattern for an injected fault is obtained when all gate modules in the ATPG neural network are stabilized through evolution and mutual interactions. The proposed methodology is efficient for test generation, known to be NP-complete, through its massive paralelism. Some results on combinational logic circuits confirm the feasibility of the proposed methodology.