• Title/Summary/Keyword: Multistage

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A study on multistage nonblocking network (다중 전송 다단계 네트워크에 관한 연구)

  • Cho, Sok-Pal
    • The Journal of Information Technology
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    • v.7 no.3
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    • pp.119-126
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    • 2004
  • In multicast traffic, an input can request to connect to up to a certain number of outputs. This reviews the multicast nonblocking multistage interconnection networks. In a multistage interconnection network each stage consists of crossbars of the same size. This paper focuses on the three-stage network and its recursive extensions. Not only will this article bring the literature upto date, but it also will provide some fresh viewpoints to either clarify or simplify some issues.

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Sample size determination using design effect formula for repeated surveys (반복조사에서 설계요소를 반영한 표본수 결정)

  • Park, Inho;Hwang, Hyeon Gil
    • The Korean Journal of Applied Statistics
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    • v.32 no.4
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    • pp.643-652
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    • 2019
  • We propose a method for sample size determination using design effect formulas when a sample is resigned for a repeated survey. The proposed method enables the determination of the sample size by incorporating the impact of various design components to the sampling error through design effect formulas that are applicable under multistage sampling design and stratified multistage sampling designs.

Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

  • Mohammad Ali Bandari;Mohammad Bagher Tavakoli;Farbod Setoudeh;Massoud Dousti
    • ETRI Journal
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    • v.45 no.4
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    • pp.690-703
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    • 2023
  • Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

Pollutants Removal Efficiency of Rainfall-runoff from Dense Highland Field Areas in Multistage Sedimentation Basins - Focused on Jaun Area in Upstream Watershed of Lake Soyang - (고랭지 밭 밀집지역 다단계 침사지의 강우-유출 오염물질 제거 효율 - 소양호 상류의 자운지구를 중심으로 -)

  • Cho, Jae Heon
    • Journal of Environmental Impact Assessment
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    • v.27 no.2
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    • pp.170-180
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    • 2018
  • Highland fields are concentrated in the Jaun area of Hongcheong-gun, a large amount of sediments are discharged from the highland fields. The sediment runoff affect the turbidity and water quality of the Soyang Lake, furthermore adversely affect water supply source of the capital region. There are several kinds of BMPs(Best management practices) to decrease the sedimentrunoff from the highland fields. Although construction cost of multistage sedimentation basins is very high, there is no actual survey data for the removal efficiency of suspended sediments and water quality in our country. In this study, stormwaterinflow and outflow of the multistage sedimentation basins were surveyed, and the removal efficiency of nonpoint source pollutants were analyzed. The stormwater survey results fortwo rainfall events show thatremoval efficiencies of SS, BOD and TP loads in the multistage sedimentation basins are 35%~62%, 24%~55%, 35%~58%, respectively. Although the measured efficiencies of the basins were lower than the theoretical efficiency, the proper operation and management can improve the removal rate of the basins. Turbid water problem in the upper parts of the Soyang River can be managed effectively through the additional installation of multistage sedimentation basins.

Performance Study of Packet Switching Multistage Interconnection Networks

  • Kim, Jung-Sun
    • ETRI Journal
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    • v.16 no.3
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    • pp.27-41
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    • 1994
  • This paper provides a performance study of multistage interconnection networks in packet switching environment. In comparison to earlier work, the model is more extensive - it includes several parameters such as multiple-packet messages, variable buffer size, and wait delay at a source. The model is also uniformly applied to several representative networks and thus provides a basis for fair comparison as well as selection of optimal values for parameters. The complexity of the model required use of simulation. However, a partial analytical model is provided to measure the congestion in a network.

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Design and Analysis of an Efficient Distributed Routing Algorithm in Multistage Interconnection Networks (다단계 상호 연결망에서의 효율적인 분산 라우팅 알고리듬의 설계 및 분석)

  • 손유익;안광선
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.11
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    • pp.1794-1803
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    • 1989
  • This paper presents and evaluates a distributed routing algorithm for effective routing control in circuit-switched multistage interconnection networks. The proposed method uses the distributed control based on the incividual-switching element control and it is very effective for allowing any broadcast connection from a source to arbitrary number of destinadtions. The performnace of the proposed method is analyzed and evaluated by computer simulation in terms of the normalized average time delays.

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A note on the sample size determination of sequential and multistage procedures

  • Choi, Kiheon
    • Journal of the Korean Data and Information Science Society
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    • v.23 no.6
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    • pp.1279-1287
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    • 2012
  • We particularly emphasized how to determine the number of replications with sequential and multistage procedures. So, the t-test is used to achieve some predetermined level of accuracy efficiently with loss function in the case of normal, chi-squared, an exponential distributions. We provided that the relevance of procedures are sequential procedure, two-stage procedure, modified two-stage procedure, three-stage procedure and accelerated sequential procedure. Monte Carlo simulation is carried out to obtain the stopping sample size that minimizes the risk.

Comparison of neural network algorithms for the optimal routing in a Multistage Interconnection Network (MIN의 최적경로 배정을 위한 신경회로망 알고리즘의 비교)

  • Kim, Seong-Su;Gong, Seong-Gon
    • Proceedings of the KIEE Conference
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    • 1995.11a
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    • pp.569-571
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    • 1995
  • This paper compares the simulated annealing and the Hopfield neural network method for an optimal routing in a multistage interconnection network(MIN). The MIN provides a multiple number of paths for ATM cells to avoid cell conflict. Exhaustive search always finds the optimal path, but with heavy computation. Although greedy method sets up a path quickly, the path found need not be optimal. The simulated annealing can find an sub optimal path in time comparable with the greedy method.

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Process Analysis of Precision Press Forming by the Finite Element Method (유한요소법을 활용한 정밀전자부품 성형공정 해석)

  • 양순종;변상규;최홍석;하석준;강범수
    • Proceedings of the Korean Society for Technology of Plasticity Conference
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    • 1997.10a
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    • pp.53-56
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    • 1997
  • The multistage precision forming process for aperture of electronic guns consists mainly of drawing and swaging operations. The multistage forming sequence is analyzed in view of production industry, and based on the industrial investigation. The processes are simulated by the finite element code MARC. The elastic recovery, strain and stress distribution, and the die forces are summarized.

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A Virtual Partially Shared Input-Buffered Banyan Switch Based on Multistage Interconnection Networks (MIN(Multistage Interconnection Networks)망을 이용한 가상 입력 버퍼 반얀 스위치 설계)

  • 권영호;김문기;이병호
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10c
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    • pp.301-303
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    • 2004
  • 현재 ATM 망에서 다양한 형태의 스위치 구조가 제안 되었으며 스위치 구조는 크게blocking 과 nonblocking 스위치로 나눌 수 있다. nonblocking 스위치는 버퍼의 위치에 따라 input queuing, output queuing, shared buffer switch로 나뉘며 그 중에 입력 버퍼형은 하드웨어 구현이 쉬운 장점이 있으나 HOL블로킹으로 인하여 처리 효율이 낮다는 단점이 있다. 본 논문에서는 이러한 입력 버퍼형 ATM 교환기의 문제점을 해결하기 위하여 가상적인 입력버퍼와 MUX를 이용한 입력버퍼형 반얀 스위치 모델을 제안한다.

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