• 전기의세계
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• v.35 no.7
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• pp.431-438
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• 1986

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.49-54
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• 2005

This Paper Presents a non-blocking deadlock detection scheme with immediate cycle detection in multiprocessing systems. We assume an expedient state and a special case where each type of resource has one unit and each request is limited to one resource unit at a time. Unlike the previous deadlock detection schemes, this new method takes O(1) time for detecting a cycle and O(n+m) time for blocking or handling resource release where n and m are the number of processes and that of resources in the system. The deadlock detection latency is thus minimized and is constant regardless of n and m. However, in a multiprocessing system, the operating system can handle the blocking or release on-the-fly running on a separate processor, thus not interfering with user process execution. To some applications where deadlock is concerned, a predictable and zero-latency deadlock detection scheme could be very useful.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.8
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• pp.710-718
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• 2000

Many multiprocessing systems have been developed to exploit the parallelism and to improve the performance. However, the naive multiprocessing schemes were not successful as many researchers thought, due to the heavy cost of communication and synchronization resulting from parallelization. In this paper, we will identify the reasons for the poor performance and the compiler requirements for the performance improvement. We realized that the decisions for multiprocessing should be derived by the overhead information. We applied this idea to the automatic parallelizing compiler, SUIF. We substituted the original backend of SUIF with our backend using MPI, and gave it the capability to validate parallelization decisions based on overhead parameters. This backend converts the intermediate code containing spacification of parallelizable regions into the distributed-memory based parallel program with MPI function calls without excessive parallelization that may cause performance degradation.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.93-99
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• 2017

In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

• Computational Structural Engineering
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• v.3 no.4
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• pp.29-34
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• 1990

HP의 HP/Apollo시리즈 10000 TX(Visualization System)는 고성능 RISC그래픽을 사용한 최초의 워크스테이션으로서, 아폴로의 Multiprocessing PRISM 아키텍쳐와 강력한 3D 그래픽 엔진을 채택하고 있어, 시스템의 성능과 Image Quality, Openness 및 Flexibility를 높여줌으로써, 타 제품에 비해 탁월한 성능과 기능을 제공하고 있으며, 사용자의 투자에 대한 효과를 확실히 높여주고 있다.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10b
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• pp.425-429
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• 1992

Point sets in the Euclidean and digital planes are discussed. The local necessary and sufficient conditions are suggested for pointed lattice extraction from these sets are presented. A number of theorems and corollaries are given. The regular and "almost" regular point sets are studied. The results can be used in automatic control of textured textile images by both general and multiprocessing systems.g systems.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.8
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• pp.1250-1256
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• 2017

In this research, a high-performance ultrasonic positioning system is proposed to track the positions of an indoor mobile object. Composed of an ultrasonic sender (mobile object) and a receiver (anchor), the system employs three ultrasonic time-off-flights (TOFs) and trilateration to estimate the positions of the object with an accuracy of sub-centimeter. On the other hand, because ultrasonic waves are interfered by temperature, wind and various obstacles obstructing the propagation while propagating in air, ultrasonic pulse debounce technique and Kalman filter were applied to TOF and position calculation, respectively, to compensate for the interference and to obtain more accurate moving object position. To perform tasks in real time, ultrasonic signals are processed full-digitally with a Zynq SoC, and as a software design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams. And, a hardware/software co-design is implemented, where the digital circuit portion is designed in the Zynq's fpga and the software portion is c-coded in the Zynq's processors by using the baremetal multiprocessing scheme in which the c-codes are distributed to dual-core processors, cpu0 and cpu1. To verify the usefulness of the proposed system, experiments were performed and the results were analyzed, and it was confirmed that the moving object could be tracked with accuracy of sub-cm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.8
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• pp.648-658
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• 1990

There are many methods for speed up counting in speech recongition. A multiple processing method is the one way to achieve the aim using systolic array. This arithmetic operation by the array is achieved pipelining skill. And the operation is multiprocessing by processing element(PE) that is incresing counting efficiencies. The DTW PE cell is seperated into three large blocks. "MIN" is the one block for counting accumulated minimum distance, "ADD" block calculated these minimum distances, and "ABS" seeks for the absolut values to the total sum of local distances. We have accomplished circuit design and verification about the "ADD" and "ABS" blocks, and performed total layout '||'&'||' DRC(design rule check) using 3um CMOS N-Well rule base.le check) using 3$\mu$m CMOS N-Well rule base.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.103-114
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• 1994

This paper proposes an implementation of DCT (Discrete Cosine Transform) and IDCT (Inverse DCT) using a fast DCT algorithm with shift and addition operations instead of multiplications Based on the proposed algorithm, a new VLSI architecture for the DCT and the IDCT is proposed. It shows modularity , regularity and capability for multiprocessing. Its performance is also simulated by a simulation software, "Compass". The results of the simulation provide the quality of decompression images, the increase in processing speed, representing the superiority of the proposed architecture.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.8
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• pp.1064-1073
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• 1995

On a bus-based shared memory multiprocessing system, the system bus monitoring and analysis are crucial for system integration test and performance analysis. In this paper, the design and implementation of a bus monitoring instrument for the TICOM-III system are decribed. The instrument dedicated to TICOM-III, which is called the Bus Information Procssing Unit, analyzes the bus state and measures the bus utilization. It performs many useful functions to help debugging the system, and offers a simple user interface.