• Title/Summary/Keyword: Multiplication Sign

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A Performance Evaluation of QE-MMA Adaptive Equalization Algorithm based on Quantizer-bit Number and Stepsize (QE-MMA 적응 등화 알고리즘에서 양자화기 비트수와 Stepsize에 의한 성능 평가)

  • Lim, Seung-Gag
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.21 no.1
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    • pp.55-60
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    • 2021
  • This paper relates with the performance evaluation of QE-MMA (Quantized Error-MMA) adaptive equalization algorithm based on the stepsize and quantizer bit number in order to reduce the intersymbol interference due to nonlinear distortion occurred in the time dispersive channel. The QE-MMA was proposed using the power-of-two arithmetic for the H/W implementation easiness substitutes the multiplication and addition into the shift and addition in the tap coefficient updates process that modifies the SE-MMA which use the high-order statistics of transmitted signal and sign of error signal. But it has different adaptive equalization performance by the step size and quantizer bit number for obtain the sign of error in the generation of error signal in QE-MMA, and it was confirmed by computer simulation. As a simulation, it was confirmed that the convergence speed for reaching steady state depend on stepsize and the residual quantities after steady state depend on the quantizer bit number in the QE-MMA adaptive equalization algorithm performance.

An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

  • Kamal, Hassan;Lee, Joo-Hyun;Koo, Bon-Tae
    • ETRI Journal
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    • v.33 no.5
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    • pp.695-703
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    • 2011
  • The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm (Radix-2 MBA 기반 병렬 MAC의 VLSI 구조)

  • Seo, Young-Ho;Kim, Dong-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.4
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    • pp.94-104
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    • 2008
  • In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

Performance Evaluation of DSE-MMA Blind Equalization Algorithm in QAM System (QAM 시스템에서 DSE-MMA 블라인드 등화 알고리즘의 성능 평가)

  • Kang, Dae-Soo
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.13 no.6
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    • pp.115-121
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    • 2013
  • This paper related with the DSE-MMA (Dithered Sign-Error MMA) that is the simplification of computational arithmetic number in blind equalization algorithm in order to compensates the intersymbol interference which occurs the passing the nonlinear communication channel in the presence of the band limit and phase distortion. The SE-MMA algorithm has a merit of H/W implementation for the possible to reduction of computational arithmetic number using the 1 bit quantizer in stead of multiplication in the updating the equalizer tap weight. But it degradates the overall blind equalization algorithm performance by the information loss at the quantization process compare to the MMA. The DSE-MMA which implements the dithered signed-error concepts by using the dither signal before qualtization are added to MMA, then the improved SNR performance which represents the roburstness of equalization algorithm are obtained. It has a concurrently compensation capability of the amplitude and phase distortion due to intersymbol interference like as the SE-MMA and MMA algorithm. The paper uses the equalizer output signal, residual isi, MD, MSE learning curve and SER curve for the performance index of blind equalization algorithm, and the computer simulation were performed in order to compare the SE-MMA and DSE-MMA applying the same performance index. As a result of simulation, the DSE-MMA can improving the roburstness and the value of every performance index after steady state than the SE-MMA, and confirmed that the DSE-MMA has slow convergence speed which meaning the reaching the seady state from initial state of adaptive equalization filter.

A Performance Improvement of QE-MMA Adaptive Equalization Algorithm based on Varying Stepsize (Varying Stepsize를 이용한 QE-MMA 적응 등화 알고리즘의 성능 개선)

  • Lim, Seung-Gag
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.1
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    • pp.101-106
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    • 2020
  • This paper relates with the VS-QE-MMA (Varying Stepsize-Quantized Error-MMA) based on the varying stepsize for improving the equalization performance in the QE-MMA adaptive equalization algorithm that is possible to reducing the intersymbol interference occurred at channel. The SE-MMA use the high-order statistics of transmitted signal and sign of error signal. The QE-MMA was appeared for the H/W implementation easiness substitutes the multiplication and substraction into the shift and substraction in the updating the tap coefficient based on the power-of-two operation of error signal magnitude. The QE-MMA gives degradation of equalization performance due to the such simplification of arithmetic operation. For improving this problem, the propose algorithm, namely VS-QE-MMA, applies the varying stepsize of the nonlinear transformation of error signal. It was confirmed by simulation that the VS-QE-MMA gives better performance than current QE-MMA in the same channel and signal to noise ratio. As a result of simulation, the VS-QE-MMA has more better performance in the every performance index, and it was also confirmed that the varying stepsize effect can be obtained in the greater than 10dB of signal to noise ratio.

A Low-Power 2-D DCT/IDCT Architecture through Dynamic Control of Data Driven and Fine-Grain Partitioned Bit-Slices (데이터에 의한 구동과 세분화된 비트-슬라이스의 동적제어를 통한 저전력 2-D DCT/IDCT 구조)

  • Kim Kyeounsoo;Ryu Dae-Hyun
    • Journal of Korea Multimedia Society
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    • v.8 no.2
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    • pp.201-210
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    • 2005
  • This paper proposes a power efficient 2-dimensional DCT/IDCT architecture driven by input data to be processed. The architecture achieves low power by taking advantage of the typically large fraction of zero and small-valued input processing data in video and image data compression. In particular, it skips multiplication by zero and dynamically activates/deactivates required bit-slices of fine-grain bit partitioned adders within multipliers and accumulators using simple input ANDing and bit-slice MASKing. The processed results from 1-D DCT/IDCT do not have unnecessary sign extension bits (SEBs), which are used for further power reduction in matrix transposer. The results extracted by bit-level transition activity simulations indicate significant power reduction compared to conventional designs.

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A study on the improvement of a suspension system adopting a semiactive on-off damper (반능동 단속형 감쇠기를 이용한 현가장치 개선에 관한 연구)

  • 최성배;박윤식
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.12 no.5
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    • pp.959-967
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    • 1988
  • In this paper, 2-DOF vehicle suspension system with a semiactive on-off damper was studied for improving the ride comfort. It is known that a nonlinear hydraulic damper, which generates force proportional to the square of the relative velocity, can describe the actual fluid resisting type damper more properly than the traditional viscous damping model. On the other hand, hydraulic damper adoption in analysis makes the system nonlinear and causes difficulties to get the system response. In this work, time domain direct integration method was used to calculate system displacement and acceleration. first of all, the response of the suspension system experiencing a given road profile was optimized by Lagrangian multiplier method within the range of given damping coefficients. The appropriate on-loaf damping values were obtained by averaging the already calculated optimum damping coefficients from Lagrangian techniques. The criterion to control the on-off mechanism was determined by examining the suspension efficiency. It was found that the best out of practically applicable criteria is following the sign (positive and negative) of the multiplication of relative displacement and velocity. Judging from the theoretical calculations, it was proved that the semiactive on-off damper can increase suspension efficiency as much as 8-11% in object function.

Effect of Plant-growth-promoting Bacteria Inoculation on the Growth and Yield of Cucumber(Cucumis sativa L.) (식물생육촉진 세균이 오이 생육 및 수량에 미치는 영향)

  • Lee, Young-Han;Cho, Woo-Suk;Kim, Jong-Gyun;Lee, Han-Saeng;Park, Sang-Ryeol;Yun, Han-Dae
    • Korean Journal of Soil Science and Fertilizer
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    • v.30 no.2
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    • pp.196-199
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    • 1997
  • We studied the effect of inoculation of microorganisms known to produce plant growth promoting substances, on the growth and yield of cucumber(Cucumis sativa L.), through a field experiment. The microorganisms used were isolated from the forest soil and consisted of Micrococus sp., Baccilus sustilis, Enterobacter agglomerans, Baccilus megaterium, Pseudomonas putida, Cellulomonas sp. and Staphylococus xyposus. Fotr the multiplication, microorganisms were cultured in liquid media of Pseudomonas P and Sabouraud dextrose. Inoculation of microorganisms was done by spraying the culture media after the culture of them to soil and cucumber plants, three times during the growth of cucumber at the rate of 10l/ha. The inoculation of microorganisms tended to promote the growth of cucumber plant and increase the yield of it. No sign of significant improvement of soil chemical and physical properties were observed after the harvest of crop. The population of bacteria and actinomycetes tended to be higher in the inoculated plots than in not inoculated plots, while opposite was the case in the population of fungi.

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