• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.270-276
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• 2018

This paper presents a low area 256-point pipelined FFT architecture, especially for IEEE 802.16a WiMAX systems. Radix-24 algorithm and single-path delay feedback (SDF) architecture are adopted in the design to reduce the complexity of twiddle factor multiplication. A new cascade canonical signed digit (CSD) complex multipliers are proposed for twiddle factor multiplication, which has lower area and less power consumption than conventional complex multipliers composed of 4 multipliers and 2 adders. Also, the proposed cascade CSD multipliers can remove look-up table for storing coefficient of twiddle factors. In hardware implementation with Cyclone 10LP FPGA, it is shown that the proposed FFT design method achieves about 62% reduction in gate count and 64% memory reduction compared with the previous schemes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1188-1193
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• 2004

So far, there have been grossly 3 types of studies on GF(2m) multiplier architecture, such as serial multiplication, array multiplication, and hybrid multiplication. Serial multiplication method was first suggested by Mastrovito (1), to be known as the basic CF(2m) multiplication architecture, and this method was adopted in the array multiplier (2), consuming m times as much resource in parallel to extract m times of speed. In 1999, Paar studied further to get the benefit of both architecture, presenting the hybrid multiplication architecture (3). However, the hybrid architecture has defect that only complex ordo. of finite field should be used. In this paper, we propose a novel approach on developing serial multiplier architecture based on Mastrovito's, by modifying the numerical formula of the polynomial-basis serial multiplication. The proposed multiplier architecture was described and implemented in HDL so that the novel architecture was simulated and verified in the level of hardware as well as software. The implemented GF(2m) multiplier shows t times as fast as the traditional one, if we modularized the numerical expression by t number of parts.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.107-110
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• 2001

In this paper, we propose a multiplication-free DFT kernel computation technique, whose input sequences are approximated into a ring of Algebraic Integers. This paper also gives computational examples for DFT and IDFT. And we proposes an architecture of the DFT using barrel shifts and adds. When the radix is greater than 4, the proposed method has a high Precision property without scaling errors due to twiddle factor multiplication. A possibility of higher radix system assumes that higher performance can be achievable for reducing the DFT stages in FFT.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.539-546
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• 1997

In this paper, we proposed a new mehtod to analyze the performance degradation by timing jitters in the APD (avalanche photodiode) receivers of intensity modulation/direct detection digital optical communication systems where raised cosine pulse-shaping filters are used to reduce the effect of noise while minimizing intersymbol interferences. The proposed analytical method is an extension of an analytical method we have already developed for pin diode receivers, and incorporates the effects of APD's multiplication factor and resulting shot noise. Using the proposed analytical method, we derive an approximated power penalty due to timing jitters based on an assumption of Gaussian distribution for timing jitters, and compare with that of the conventional analytical method. The results obtained from the proposed analytical method show that conventional analytical methods underestimate the influence of timing jitters on the reciver performance. The results also show that APD's multiplication factor which optimizes receiver sensitivity is smaller than that obtained by the conventional analytical method.

• Nuclear Engineering and Technology
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• v.14 no.3
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• pp.138-147
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• 1982

A theoretical basis for analysis of plutonium-hearing fuel in a thermal nuclear power reactor has been established. The analysis of UO$_2$-PuO$_2$ fueled, light water moderated uniform lattice experiments has been performed. A unit cell program, KARATE, which is based on the theoretical models of GAM and THERMOS with some modifications, has been developed to generate a few-group cross-sections. These cross-sections are subsequently used in the diffusion theory code, KIDD, to compare the calculated values of the effective multiplication factor with the measured. The average value of the effective multiplication factor for 41 selected critical experiments is estimated to be 0.9997 with standard deviation of 0.43%. This illustrates the fact that KARATE/KIDD system can be effectively used for the analysis of uniform lattices of UO$_2$-PuO$_2$fuels.

• Nuclear Engineering and Technology
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• v.18 no.2
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• pp.78-84
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• 1986

An equation of material number density sensitivity coefficient is derived using first-order perturbation theory. The beginning of cycle of Super-Phenix I is taken as the reference system for this study. Effective multiplication factor of the reference system is defined as system response function and fuel enrichment and fuel effective density are chosen for the variation of reference input data since they are described by material number density which is a component of Boltzmann operator. The nuclear computational code system (KAERI-26 group cross section library/1DX/2DB/PERT-V) is employed for this calculation. Sensitivity coefficient of fuel enrichment on effective multiplication factor is 4.576 and sensitivity coefficient of effective fuel density on effective multiplication factor is 0.0756. This work shows that sensitivity methodology is lesser timeconsuming and gives more informations on important design parameters in comparison with the direct iterative calulation through large computer codes.

• Nuclear Engineering and Technology
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• v.48 no.5
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• pp.1126-1139
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• 2016

In this research, for the first time, a new optimization method, i.e., strength Pareto evolutionary algorithm II (SPEA-II), is developed for the burnable poison placement (BPP) optimization of a nuclear reactor core. In the BPP problem, an optimized placement map of fuel assemblies with burnable poison is searched for a given core loading pattern according to defined objectives. In this work, SPEA-II coupled with a nodal expansion code is used for solving the BPP problem of Kraftwerk Union AG (KWU) pressurized water reactor. Our optimization goal for the BPP is to achieve a greater multiplication factor ($K_{eff}$) for gaining possible longer operation cycles along with more flattening of fuel assembly relative power distribution, considering a safety constraint on the radial power peaking factor. For appraising the proposed methodology, the basic approach, i.e., SPEA, is also developed in order to compare obtained results. In general, results reveal the acceptance performance and high strength of SPEA, particularly its new version, i.e., SPEA-II, in achieving a semioptimized loading pattern for the BPP optimization of KWU pressurized water reactor.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.6
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• pp.736-743
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• 2020

Modular multiplication is one of the most important arithmetic operations in public-key cryptography such as elliptic curve cryptography (ECC) and RSA, and the performance of modular multiplier is a key factor influencing the performance of public-key cryptographic hardware. An efficient hardware implementation of word-based Montgomery modular multiplication algorithm is described in this paper. Our modular multiplier was designed to support eleven field sizes for prime field GF(p) and binary field GF(2k) as defined by SEC2 standard for ECC, making it suitable for lightweight hardware implementations of ECC processors. The proposed architecture employs pipeline scheme between the partial product generation and addition operation and the modular reduction operation to reduce the clock cycles required to compute modular multiplication by 50%. The hardware operation of our modular multiplier was demonstrated by FPGA verification. When synthesized with a 65-nm CMOS cell library, it was realized with 33,635 gate equivalents, and the maximum operating clock frequency was estimated at 147 MHz.

• Journal of Radiation Protection and Research
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• v.8 no.1
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• pp.33-37
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• 1983

Neutron reflecting effects in terms of effective multiplication factor have been calculated with varying water or concrete thickness, and gap distance between concrete reflector and a fissile solution system. A numerical calculation of effective multiplication factors has been carried out by using the discrete ordinates method with the help of the computer code, ANISN. It is revealed that the reflecting .effect by thin concrete is lower than that of the identical thickness of water while the effect by thick water is low compared to that of the identical thickness of concrete. It seems that the effective multiplication factors are first decreasing rapidly with gap distance, which is filled with water, between concrete reflector and the fissile solution system, and then decrease slowly over the distance of about 15cm.

• Proceedings of the Korean Nuclear Society Conference
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• 2002.05a
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• pp.52-52
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• 2002