• Journal of the Korean Society for Precision Engineering
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• v.20 no.3
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• pp.221-229
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• 2003

In the early phases of the product life cycle, Life Cycle Assessment (LCA) is recently used to support the decision-making fer the conceptual product design and the best alternative can be selected based on its estimated LCA and its benefits. Both the lack of detailed information and time for a full LCA fur a various range of design concepts need the new approach fer the environmental analysis. This paper suggests a novel approximate LCA methodology for the conceptual design stage by grouping products according to their environmental characteristics and by mapping product attributes into impact driver index. The relationship is statistically verified by exploring the correlation between total impact indicator and energy impact category. Then a neural network approach is developed to predict an approximate LCA of grouping products in conceptual design. Trained learning algorithms for the known characteristics of existing products will quickly give the result of LCA for new design products. The training is generalized by using product attributes for an ID in a group as well as another product attributes for another IDs in other groups. The neural network model with back propagation algorithm is used and the results are compared with those of multiple regression analysis. The proposed approach does not replace the full LCA but it would give some useful guidelines fer the design of environmentally conscious products in conceptual design phase.

• Journal of the Korean Wood Science and Technology
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• v.46 no.4
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• pp.380-392
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• 2018

The importance of polysaccharides is increasing globally due to their role as a significant source of dietary prebiotics in the human diet. In the present study, in order to maximize the yield of crude polysaccharides from Pinus densiflora, response surface methodology (RSM) was used to optimize a two-stage extraction process consisting of steam explosion and water extraction. Three independent main variables, namely, the severity factor (Ro) for the steam explosion process, the water extraction temperature ($^{\circ}C$), and the ratio of water to raw material (v/w), were studied with respect to prebiotic sugar content. A Box-Behnken design was created on the basis of the results of these single-factor tests. The experimental data were fitted to a second-order polynomial equation for multiple regression analysis and examined using the appropriate statistical methods. The data showed that both the severity factor (Ro) and the ratio of water to material (v/w) had significant effects on the prebiotic sugar content. The optimal conditions for the two-stage process were as follows: a severity factor (Ro) of 3.86, a water extraction temperature of $89.66^{\circ}C$, and a ratio of water to material (v/w) of 39.20. Under these conditions, the prebiotic sugar content in the extract was 332.45 mg/g.

• Industrial Engineering and Management Systems
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• v.9 no.1
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• pp.41-53
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• 2010

An existing risk diagnosing methodology (RDM) diagnoses corporate risk for product-innovation projects. However, it cannot evaluate and compare the risk levels of multiple alternatives in the product development stage. This paper proposes a modified risk diagnosis method to fill the gap of risk evaluation in selections of innovative product alternatives and the application of the method will be also illustrated by a case problem on alternative selections in electrical dimmer designs. With RDM as the foundation, a modified RDM (MRDM) is proposed to deal with the problem of selecting innovative project alternatives during the early stages of product development. The Bayesian network; a probabilistic graphical model, is adopted to support the risk pre-assessment stage in the MRDM. The MRDM is proposed by incorporating the risk pre-assessment stage into the foundation. By evaluating the engineering design risks in two electrical dimmer switches, an application of the MRDM in product innovation development is successfully exemplified. This paper strengthens the existing methodology for RDM in innovative product development projects to accommodate innovative alternatives. It is advantageous for companies to identify and measure the risks associated in product development so as to plan for appropriate risk mitigation strategies.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.4
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• pp.930-937
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• 2007

In this paper, we address a design problem and a case study of a K-stage inspection system, which is composed of K stages, each of which includes an inspection process and a rework process. Assuming the type I and II errors of inspectors and the re-inspection policy for items classified as good, we determine the smallest integer of K which can achieve a given target defective rate. If K does not exist, holding the current values of the type I, II errors, we search reversely a new vector, (the defective rate of an assembly line, the defective rate of a rework process), which can give the target defective rate. Our formulas and methodology based on our K-stage inspection system could be applied and extended to similar situations with slight modifications.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.112.1-112.1
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• 2010

To develop domestic IGCC gasification technology, a gasification test bed with a capacity of 20 tons/day has been designed. The main components of the test bed designed are a coal pulverizing and feeding facility, a gasifier, a syngas cooler, a gas treatment unit, oxygen and nitrogen tanks, and flare stack. For wide applications to the development of advanced coal gasification technology, many special functions have been given to it such as syngas recirculation, char recirculation, and multiple stage gasification. The test bed will be used for testing the characteristics of various types of coals, deriving optimum conditions for efficient gasifier operation and trouble shooting for the Korea IGCC demonstration plant. It will also be applied as a useful tool to develop scale-up design technology of IGCC and proceed to commercialization.

• Journal of IKEEE
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• v.16 no.3
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• pp.197-202
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• 2012

As more and more cores are integrated on a single chip, power consumption has become an important problem in system-on-a-chip (SoC) design. Multiple supply voltage (MSV) design is one of popular solutions to reduce power consumption. We propose a new method that determines voltage level of cores before floorplanning stage. Besides, our algorithm includes a new approach to optimize wire length and the number of level shifters without any significant decrease of power saving. In simulation, we achieved 40-52% power saving and a considerable improvement in runtime, whereas an increase in wire length and area is less than 8%.

• Journal of the Korean housing association
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• v.8 no.1
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• pp.77-85
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• 1997

The purpose of this study was to estimate the quality if New Town housing environment, and to present the direction of design policy to elevate it. For this study questionnaires were administrated to 272 homemakers living in apartment in Bundang. From 1st of May to 31st of May in 1995. Used statistical method was Frequency. Percentage. Mean, Factor Analysis, Correlation, Multiple Regression. The major finding is as follows : 1) Housing values were classified into five types : convenience, beauty, sociality, education, and economy, Resident ranked first economy among housing values the second is convenience, the third beauty, the forth education, while the most unimportant value is sociality. 2) House satisfaction was classified into four types : house size and plane structure, environment and facilities, interior decoration materials and facilities and building design. Residents were found to show the middle degree satisfaction on their house. 3) Housing complex satisfaction was ciassified four types : community facilities, management stage, neighborhood connection and complex facilities. Resident showed dissatisfaction on their apartment complex relatively. 4) Residents showed dissatisfaction on the interior decoration materials and facilities, local facilities and management attitude relatively.

• Proceedings of the Korea Concrete Institute Conference
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• 2004.05a
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• pp.40-43
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• 2004

A new design method for prestressed concrete girder is proposed in this study, which steps for manufacturing are; (1) the bottom part of concrete girder is placed and pretensioned by the first post-tensioning performed on the tendons located in the bottom part of concrete girder, and (2) the next step which consists of concrete placing and post-tensioning operation is followed by the previous step if required. This indicates that sufficient compressive stress can be effectively introduced at the bottom face in stepwise manner, when compared to conventional PSC girder. Two specimens are prepared and tested to investigate the short-term behavior of the PSC girders manufactured by the proposed method. Section Analysis results exhibit good agreements with the test results in terms of strain distribution across the girder section. In addition, flexural strength obtained from the tests is found to be similar to the expected based on Code(Korea). These demonstrate that the method proposed in this study is applicable to the design of PSC girders.

• Journal of information and communication convergence engineering
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• v.12 no.1
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• pp.46-52
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• 2014

This article presents key research needs in three-dimensional integrated circuit (3D IC) architectural floorplanning. Architectural floorplaning is done at a very early stage of 3D IC design process, where the goal is to quickly evaluate architectural designs described in register-transfer level (RTL) in terms of power, performance, and reliability. This evaluation is then fed back to architects for further improvement and/or modifications needed to meet the target constraints. We discuss the details of the following research needs in this article: block-level modeling, through-silicon-via (TSV) insertion and management, and chip/package co-evaluation. The goal of block-level modeling is to obtain physical, power, performance, and reliability information of architectural blocks. We then assemble the blocks into multiple tiers while connecting them using TSVs that are placed in between hard IPs and inside soft IPs. Once a full-stack 3D floorplanning is obtained, we evaluate it so that the feedback is provided back to architects.