• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.191-200
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• 2002

In this paper, we present the method transforming the interval functions into the truncated difference functions for multi-variable multi-valued functions and implementing the truncated difference functions to the multiple valued logic circuits with uniform patterns using the current mirror circuits and the inhibit circuits by current-mode CMOS. Also, we apply the presented methods to the implementation of circuits for additive truth table of 2-variable 4-valued MOD(4) and multiplicative truth table of 2-variable 4-valued finite fields GF(4). These circuits are simulated under 2${\mu}{\textrm}{m}$ CMOS standard technology, 15$mutextrm{A}$ unit current, and 3.3V power supply voltage using PSpice. The simulation results have shown the satisfying current characteristics. Both implemented circuits using current-mode CMOS have the uniform Patterns and the regularity of interconnection. Also, it is expansible for the variables of multiple valued logic functions and are suitable for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.5
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• pp.1-7
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• 1983

Generally, multiple-valued logic algebra is based on the number system of modulo-M. In this paper, characters a, b, c‥… each of them represents the independent state, are regarded as the elements of the symbolic multiple-valued logic. By using the set theory, the symbolic multiple - valued logic and their functions are defined. And Varation for the symbolic logic function due to the variation of a variable and their properties are suggested and analized. With these variations, the MacLaurin's and Taylor's Series expansions of the symbolic logic functions are proposed and proved.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.1
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• pp.13-18
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• 2009

Usually, human emotions are vague and change diversely on the basis of the stimulus from the outside. Plutchik classified the fundamental behavioral patterns into eight patterns, named each of them a genuine emotion, and furthermore suggested mixed emotions using a combination of genuine emotions. In this paper, we propose a method for processing Plutchik's emotion model using Multiple Valued Logic(MVL) Automata Model which utilizes the properties of difference in Multiple Valued Logic functions. This proposed emotion processing model can be widely applied to the analysis and processing of emotion data.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.56-64
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• 1992

The sum-of-product type MVL (Multiple-valued logic) functions can be directly transformed into the exclusive-sum-of-literal-product(ESOLP) type MVL functions with a substitution of the OR operator with the exclusive-OR(XOR) operator. This paper presents an algorithm that can reduce the number of minterms for the purpose of minimizing the hardware size and the complexity of the circuit in the realization of ESOLP-type MVL functions. In Boolean algebra, the joinable true minterms can form the cube, and if some cubes form a cube-chain with adjacent cubes by the insertion of false cubes(or, false minterms), then the created cube-chain can become a large cube which includes previous cubes. As a result of the cube grouping, the number of minterms can be reduced artificially. Since ESOLP-type MVL functions take the MIN/XOR structure, a XOR circuit and a four-valued MIN/XOR dynamic-CMOS PLA circuit is designed for the realization of the minimized functions, and PSPICE simulation results have been also presented for the validation of the proposed algorithm.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.111-119
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• 1997

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently used in constructing the digital logic systems based on the graph theory. And we discussed the function minimization method of the n-variables multiple-valued functions. The proposed method has the visible, schematical and regular properties.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.69-78
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• 1998

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently using in constructing the digital logic systems based on the graph theory. We discussed the function minimization method of the n-variables multiple-valued functions and showed that the algorithm had the regularity with module by which the same blocks were made concerning about the schematic property of the proposed algorithm. We showed the EMVDD of Full Adder by module construction and verified the proposed algorithm by examples. The proposed method has the visible, schematical and regular properties.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.295-308
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• 1986

This paper presents a method of constructing multiple-valued logic functions based on Galois field. The proposed algorithm assigns all elements in GF(2**m) to bit codes that are easily converted binary. We have constructed an adder and a multiplier using a multiplexer after bit code operation (addition, multiplication) that is performed among elements on GF(2**m) obtained from the algorithm. In constructing a generalized multiple-valued logic functions, states are first minimized with a state-transition diagram, and then the circuits using PLA widely used in VLSI design for single and multiple input-output are realized.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• Journal of the Korean Institute of Telematics and Electronics
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• v.17 no.2
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• pp.29-36
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• 1980

This paper presents a method for constructing multiple- valued switching functions based on Galois fields. First the constructing Inethod for single- variable switching functions is developers and the results are extended to multiple- variable functions. The fundalnental Inathelnatical properties used in this paper are. (1) The sum of all elements over CF of is zero. (2) The Product of nonzero elements over GF(N) is equal to e1 for Neven, and e1( ) for N odd. With these properties, a relatlvely simple constructing method is developed, and a process for determining the coefficients of the expanded forms of switching functions is also obtained without successive multiplication of the polynomials. Some examples are given to illustrate the method.