• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.903-917
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• 2012

For transmitting sensed data, wireless sensor networks have been developed and researched for the improvement of energy efficiency, hence, many MAC protocols in WSN employ the duty cycle mechanism. Since the progressed development of the low power transceiver and processor let the high energy efficiency come true, the delivery of the multimedia data which occurs in area of sensor work should be needed to provide supplemental information. In this paper, we design a new scheme for massive transmission of large multimedia data where the duty cycle is used in contention based MAC protocol, for WMSN. The proposed scheme can be applied into the previous duty cycle mechanism because it provides two operation between normal operation and massive transmission operation. Measuring the buffer status of sender and the condition of current radio channel can be criteria for the decision of the above two operations. This paper shows the results of the experiment by performing the simulation. The target protocol of the experiment is X-MAC which is contention based MAC protocol for WSN. And two approaches, both X-MAC which operates only duty cycle and X-MAC which operates combined massive transmission scheme, are used for the comparative experiment.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.658-672
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• 2004

Multimedia applications are required to process the huge amount of data at high speed in real time. The memory reference instructions such as loads and stores are the main factor which limits the high speed execution of processor. To enhance the memory reference speed, cache prefetch schemes are used so as to reduce the cache miss ratio and the total execution time by previously fetching data into cache that is expected to be referenced in the future. In this study, we present an advanced data cache prefetching scheme that improves the conventional RPT (reference prediction table) based scheme. We considers the cache line size in calculation of the address stride referenced by the same instruction, and enhances the prefetching algorithm so that the effect of prefetching could be maintained even if an irregular address stride is inserted into the series of uniform strides. According to experiment results on multimedia benchmark programs, the cache miss ratio has been improved 29% in average compared to the conventional RPT scheme while the bus usage has increased relatively small amount (0.03%).

• Journal of Broadcast Engineering
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• v.10 no.4 s.29
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• pp.528-539
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• 2005

The H.264 has been adopted as the video codec for various multimedia services such as DMB and next-generation DVD because of its superior coding performance. However, the reference codec of the standard, the joint model (JM) contains quite a few algorithms which are too complex to be used for the resource-constraint embedded environment. This paper introduces very low-complexity H.264 encoding algorithm which is applicable for the embedded environment. The proposed algorithm was realized by restricting some coding tools on the basis that it should not cause too severe degradation of RD-performance and adding a few early termination and bypass conditions during the motion estimation and mode decision process. In case of encoding of 7.5fps QCIF sequence with 64kbpswith the proposed algorithm, the encoder yields worse PSNRs by 0.4 dB than the standard JM, but requires only $15\%$ of computational complexity and lowers the required memory and power consumption drastically. By porting the proposed H.264 codec into the PDA with Intel PXA255 Processor, we verified the feasibility of the H.264 based MMS(Multimedia Messaging Service) on PDA.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.1
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• pp.15-21
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• 2010

This paper proposes the multimedia fingerprinting code insertion algorithm when video content is distributed in P2P environment, and designs the collusion codebook SRP(Small RISC Processor) embedded system for the collusion attack prevention. In the implemented system, it is detecting the fingerprinting code inserted in the video content of the client user in which it requests an upload to the web server and in which if it is certified content then transmitted to the streaming server then the implemented system allowed to distribute in P2P network. On the contrary, if it detects the collusion code, than the implemented system blocks to transmit the video content to the streaming server and discontinues to distribute in P2P network. And also it traces the colluders who generate the collusion code and participates in the collusion attack. The collusion code of the averaging attack is generated with 10% of BIBD code v. Based on the generated collusion code, the codebook is designed. As a result, when the insert quantity of the fingerprinting code is 0.15% upper in bitplane 0~3 of the Y(luminance) element of I-frame at the video compression of ASF for a streaming service and MP4 for an offline offer of video content, the correlation coefficient of the inserted original code and the detected code is above 0.15. At the correlation coefficient is above 0.1 then the detection ratio of the collusion code is 38%, and is above 0.2 then the trace ratio of the colluder is 20%.

• Journal of Broadcast Engineering
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• v.13 no.4
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• pp.452-462
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• 2008

In this paper, we address issues associated with the real-time implementation of the MPEG-1/2 Layer-II (or MUSICAM) and MPEG-4 ER-BSAC decoders for Digital Multimedia Broadcasting (DMB) on TMS320C64x+ that is a fixed-point DSP processor with a clock speed of 330 MHz. To achieve the real-time requirement, they should be optimized in different steps as follows. First of all, a C-code level optimization is performed by sharing the memory, adjusting data types, and unrolling loops. Next, an algorithm level optimization is carried out such as the reconfiguration of bitstream reading, the modification of synthesis filtering, and the rearrangement of the window coefficients for synthesis filtering. In addition, the C-code of a synthesis filtering module of the MPEG-1/2 Layer-II decoder is rewritten by using the linear assembly programming technique. This is because the synthesis filtering module requires the most processing time among all processing modules of the decoder. In order to show how the real-time implementation works, we obtain the percentage of the processing time for decoding and calculate a RMS value between the decoded audio signals by the reference MPEG decoder and its DSP version implemented in this paper. As a result, it is shown that the percentages of the processing time for the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders occupy less than 3% and 11% of the DSP clock cycles, respectively, and the RMS values of the MPEG-1/2 Layer-II and MPEG-4 ER-BSAC decoders implemented in this paper all satisfy the criterion of -77.01 dB which is defined by the MPEG standards.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.55-65
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• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.

• Journal of Korea Multimedia Society
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• v.14 no.2
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• pp.249-257
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• 2011

To protect the market for various products, existing authentication techniques using ID, hologram and RFID have been gradually developed. However, these methods can be easily exposed the authentication information, and also these exposed information easily copy. Thus, production of the counterfeit goods can not completely prevent. In this paper, to solve these problems, we designed JCVM file system for saving and managing the authentication information, user's information and a sales agency information into the smart card. And we designed and implemented an authentication protocol that can authenticate to avoiding exposure using processor of the smart card. Through this, this proposed scheme can prevent occurrences of the counterfeit goods. And also, can be used for authentication as any product that can attach the smart card.

• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1189-1199
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• 2003

This paper presents a new method for the motion detection of vehicles using hierarchical motion estimation and parallel processing. It captures the road image by using a CMOS sensor. It divides the captured image into small blocks and detects the motion of each block by using a block-matching method which is based on a hierarchical motion estimation and parallel processing for the real-time processing. The parallelism is achieved by using tile pipeline and the data flow technique. The proposed method has been implemented by using an embedded system. The proposed block matching algorithm has been implemented on PLDs(Programmable Logic Device) and clustering algorithm has been implemented by ARM processor. Experimental results show that the proposed system detects the motion of vehicles in real-time.

• Journal of Korea Multimedia Society
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• v.5 no.3
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• pp.342-350
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• 2002

The execution speed is not an important factor for Java programming language when implementing small size application program which is executed on the web browser, but it becomes a serious limitation when the huge-size programs are implemented. To overcome this problem, the various research is conducted for translating the Bytecode into the target code which can be implemented in the specific processor by using classical compiling methods. In this research, we have designed and realized an intermediate code translator for the native code generation system with which we can directly generate i386 code from Bytecode to improve the execution speed of Java application programs. The intermediate code translator generates the register-based intermediate code from *.class files which are the intermediate code of Java.

• Journal of Korea Multimedia Society
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• v.14 no.7
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• pp.940-948
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• 2011

In this paper, we design and implement a task scheduler that considers real-time and fault tolerance in embedded system with a single processor. We propose a method how it can meet the deadlines of periodic tasks using RMS and complete the execution of aperiodic tasks by calculating surplus times from a periodic task set. And we describe a method how to recover of a transient fault task by managing backup time. We propose an important level of periodic tasks that can control the response time of periodic and aperiodic tasks. Finally, we analyse and evaluate the proposed methods by simulation.