• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1567-1570
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• 2002

This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70％ of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.389-393
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• 2008

OFDM (Orthogonal Frequency Division Multiplexing) modulation using the orthogonal subcarriers reduces the delay spread by increasing robustness to multipath fading and can use overlapped bandwidth due to orthogonality on frequency domain. Thus data rate and spectral efficiency are increased. Because of these reason, OFDM is used for high speed data transmission for multimedia transmission as HSDPA, WiBro, WLAN. However OFDM also has drawbacks that have the high PAPR (Peak to Average Power Ratio). This high PAPR takes place because of parallel processing a number of data at once using a FFT processor. By high PAPR, amplifier doesn't act in dynamic range, so that BER performance is worse. In this paper, we reduce the PAPR using SLM(Selective Mapping). SLM doesn't effect on BER performance, but should transmit the side information for demodulation [2]. Also PAPR is higher as the number of FFT processor is larger. Thus SLM has high complexity. In this paper, we analyze the performance of SLM using scaling for no side information.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1211-1217
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• 2005

Current generation embedded systems are built around only a small number of SOCs, which are again based on general-purpose embedded micro-processors, such as ARM and MIPS. These RISC-based processors are not, however, designed for specific functions such as networking and multimedia processing, whose importances have increased dramatically in recent years. Network devices for small business and home networks, are especially dependent upon such SOCs based on general processors. Except for PHY and MAC layer functions, which are built with hardware, all the network functions are processed by the embedded micro-processor. Enabling technologies such as VDSL and FTTH promise Internet access with a much higher speed, while at the same time explore the limitations of general purpose microprocessors. In this paper we design a network processor, embed it into an SOC for Home gateway, evaluate the performance rigorously, and gauge a possibility for commercialization.

• Journal of IKEEE
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• v.15 no.4
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• pp.345-353
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• 2011

Recently portable mobile devices such as smart-phones and notebooks have rapidly increasing demands. Those devices consume more power because they are expected to offer more complex functionality including multimedia features. For these reasons engineering efforts are changing to focus on maximizing energy efficiency within a limited battery capacity instead of increasing computational performance. In this paper, we propose a battery management system using event driven programming technique on a embedded processor. We also show that the proposed system satisfies SBS (Smart Battery Specification) v1.1. The proposed system maintains minimum code size and memory size comparing to those of RTOSs. The proposed system can be also easily incorporated in the conventional RTOSs as a form of firmware.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.225-228
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• 2004

Digital contents is used already in near place with us. Contents of MPEG-4 standard is used to process multimedia data in field of communication, computer, broadcasting mobile etc. However, absence of copyright management and protection system and interoperability problem of right system between each corporation happened. Because MPEG establish IPMP(Intellectual Property Management and Protection) system standard in agreement with MPEG-4 system standard, proposed cooperation method to manage and protect copyright. Accordingly, in this paper, put in copyright of authorized contents management and protection extension system implementation adding MPEG-4 IPMP system like plug-in into existing MPEG-4 authorizing tool. Therefore, author edits IPMP information to protect contents or object, and process the information in system and authorize MPEG-4 digital contents that have management and protection sign according to IPMP standard. This system designed and implemented to divided into IPMP information save processor, IPMP information creation processor, media IPPM processor, XMT-A to MP4 converter IPMP extension.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.6
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• pp.99-105
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• 2022

This paper deals with the problem of appropriately allocating multiple processors arriving at the ready queue to the block in the user space of the main memory is divided into blocks of variable size at compilation time. The existing allocation methods, first fit(FF), best fit(BF), worst fit(WF), and next fit(NF) methods, had the disadvantage of waiting for a specific processor because they failed to allocate all processors arriving at the ready queue. The proposed algorithm in this paper is a simple block packing algorithm that allocates as many processors as possible to the largest block by sorting the size of the partitioned blocks(holes) and the size of the processor in the ready queue in descending order. The application of the proposed algorithm to nine benchmarking experimental data showed the performance of allocating all processors while having minimal internal fragment(IF) for all eight data except one data in which the weiting processor occurs due to partition errors.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.454-461
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• 2007

Portable embedded systems have recently become smaller in size and offer a variety of junctions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.

• Journal of Korea Multimedia Society
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• v.3 no.5
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• pp.526-534
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• 2000

There have been many researches on the 3D graphic accelerator for high speed by needs of CAD/CAM,3D modeling, virtual reality or medical image. In this paper, an SIMD processor architecture for 3D graphic accelerator is proposed in order to improve the processing time of the 3D graphics, and a parallel Phong shading algorithm is presented to estimate performance of the proposed architecture. The proposed SIMD processor architecture for 3D graphic accelerator consists of PCI local bus interface, 16 Processing Elements (PE's), and Park's multi-access memory system (NAMS) that has 17 memory modules. A serial algorithm for Phong shading is modified for the architecture and the main key is to divide a polygon into $4\times{4}$ squares. And, for processing a square, 4 PE's are regarded as a PE Grou logically. Since MAMS can support block access type with interval 1, it is possible that 4 PE Groups process a square at a time. In consequence, 16 pixels are processed simultaneously. The proposed SIMD processor architecture is simulated by CADENCE Verilog-XL that is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed enhancement by the parallel algorithm to the serial one is 5.68.

• Journal of Korea Multimedia Society
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• v.13 no.10
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• pp.1525-1533
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• 2010

With the digital terrestrial television broadcasting transition, terrestrial television broadcasting have required the replacement of retransmission facilities for the analog broadcasting installed in the existing apartment, building, cable TV station, MATV system and so on. In addition, new standards have been enacted for retransmission of the digital television broadcasting in MATV system. To deal with this issue, in this paper, we propose a new 8-VSB remodulator that can retransmit signals of the terrestrial digital television broadcasting. Moreover, we present a standard and the process composition of the 8-VSB remodulator, and an experimental environment configuration for performance evaluation. To achieve this, we have implemented the 8-VSB remodulator with the sequential process components comprised of the RF signal retransmission, the TS stream modulator, the RF signal reception and demodulation. Through the simulation, we analyze the performance standard from the measured data such as spurious and phase noise. And then, we measure SNR and EVM of each attenuation step of the signal obtained by the signal processor and the 8-VSB remodulator with the same retransmission environment and conditions. Experimental results show that both the 8-VSB remodulator and the signal processor can be used as equipment for the retransmission of the terrestrial digital television broadcasting. In addition, the 8-VSB remodulator performed well to improve the transmission efficiency for the digital broadcasting signal, compare to the existing signal processor.

• Journal of the Korea Computer Graphics Society
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• v.17 no.2
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• pp.37-43
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• 2011

OpenVG and SVG Tiny are the most widely used 2D vector graphics technologies for outputs in the various embedded environments including smart phones. Especially, to show high refresh rates on the high resolution screens, it is necessary to effectively accelerate them. Until now, OpenVG and SVG Tiny are available as hardware implementations such as the fully-dedicated graphics chips or full software implementations. Currently available vector graphics silicon chips are relatively expensive and require high power consumption. In contrast, previous full software implementations show lower performance even with almost 100% CPU usages, which would disrupt other multi-threaded applications, In this paper, we present a cost-effective way of accelerating both of OpenVG and SVG Tiny, based on the multimedia-processing hardware, which is wide-spread on the media devices and mobile phones. Through the effective use of these multimedia processors, we successfully accelerated OpenVG and SVG Tiny at least 3.5 times to at most 30 times, even with lower power consumption and lower CPU usage.