• Journal of Navigation and Port Research
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• v.37 no.4
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• pp.375-381
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• 2013

In order to establish eLoran system it needs the betterment of a receiver and a transmitter, the add of data channel to loran pulse for loran system information and the differential Loran for compensating Loran-c signal. Precise ASF database map is essential if the Loran delivers the high absolute accuracy of navigation demanded at maritime harbor entrance. In this study we developed the ASF mapping method using predicted ASFs compensated by the measured ASFs for maritime in the harbor. Actual ASF is measured by the legacy Loran signal transmitted from Pohang station in the GRI 9930 chain. We measured absolute propagation delay between the Pohang transmitting station and the measurement points by comparing with the cesium clock for the calculation of the ASFs. Monteath model was used for the irregular terrain along the propagation path in the Yeongil Bay. We measured the actual ASFs at the 12 measurement points over the Yeongil Bay. In our ASF-mapping method we estimated that the each offsets between the predicted and the measured ASFs at the 12 spaced points in the Yeongil. We obtained the ASF map by adjusting the predicted ASF results to fit the measured ASFs over Yeungil bay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.