• Proceedings of the Korea Multimedia Society Conference
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• 2001.06a
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• pp.219-222
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• 2001

본 연구의 내용은 실시간 서비스 트래픽, 즉 보장형 서비스를 위한 스케줄링 알고리즘들에 대한 성능분석에 대한 연구이다. 특히 실시간 데이터 전송의 경우, 작은 지연 시간을 요구하면서 안정된 QoS를 요구하고 있다. 기존에 알려진 FQ, WFQ, WF2Q, Virtual Clock 스케줄링 알고리즘들을 사용해서 대기 큐의 수학적 모델이 아닌 시뮬레이션 도구를 사용해서, 지연에 민감한 보장형 서비스 트래픽에 대한 시간 복잡도, 공정성, 처리율 측면으로 성능을 분석하였다.

• Proceedings of the Korea Multimedia Society Conference
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• 1998.04a
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• pp.333-338
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• 1998

본 논문에서는 AAL-2/ATM 통신망 환경에서 멀티미디어 통신을 구현하기 위한 멀티미디어 동기화 기능으로 VGC 기반의 SRTS/AAL-2를 제안한다. 제안된 멀티미디어 동기화 알고리즘에서는 가변 비트율 멀티미디어 정보의 클럭 주파수 복원을 위하여 VGC(Virtual Global Clock)을 구성하고, 이를 기반으로 한 SRTS방식의 미디어 내부 동기와, MM-SSCFS(Multimedia-SSCS)/AAL-2 프로토콜을 사용한 미디어 간의 동기를 유지하는 방법을 제안하였다. 본 논문의 실험 환경으로는 Fore ATM 교환기(155 Mbps $\times$8 port)를 사용해서 소규모 B-ISDN/ATM 통신망을 구성하였고, SUN Workstatin Solaris 2.5에 접속된 Fore ATM 접속 카드 SBA-200에서 지원하는 XTI(X/Opne Transport Interface)-API를 사용하였다.

• Journal of Korea Multimedia Society
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• v.15 no.11
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• pp.1391-1398
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• 2012

Time synchronization is crucial in wireless sensor networks such as Wireless USB and WBAN for diverse purposes from the MAC to the application layer. This paper proposes online clock skew estimators to achieve energy-efficient time synchronization for wireless sensor networks. By using recursive least squares estimators, we not only reduce the amount of data which should be stored locally in a table at each sensor node, but also allow offset and skew compensations to be processed simultaneously. Our skew estimators can be easily integrated with traditional offset compensation schemes. The results of simulation and experiment show that the accuracy of time synchronization can be greatly improved through our skew compensation algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.69-74
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• 2003

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless Multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFTT after the getting the frequency, response of deducted channel from channel deducted of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of ${\pm}$ 1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.44-55
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• 2001

MAC(Multiply and ACcumulate) is the core operation of multimedia data processing. Because MAC units implemented on traditional DSP units or embedded processors have latency of three cycles and cannot operate on multiple data simultaneously, then, performances are seriously limited. Many high end general purpose microprocessors have SIMD MAC unit as a functional unit. But these high end MAC units must support pipeline structure for various operation modes and high clock frequency, which makes control logic complex and increases chip area. In this paper, a 64bit SIMD MAC unit for embedded processors is designed. It is implemented to have a latency of one clock cycle to remove pipeline control logics and a minimal area overhead for SIMD support is added to existing Booth multipliers.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.363-376
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• 1997

In this paper, we present a hardware architecture and a sofrware architecture for cimputer based teleconferencing systems.And also we analyse stream adtivation mechanisms for them form the viewpoint of delay. MuX that is a multimedia I/O server provides various processing elements for data I/O, synchronization, interleaving and mixing.We describe methods to build teleconferencing systems with the elements and compares the technique using master click with the techniquie using self clock.In the plase of dta input.the technique using self click is berrer than the technique using master clock.When we generate interleved stream from audio and video stream and activate channel objects by periodic audio stream as activation clock, dealy from imput audio stream to imterleved stream is reduced but delay for video stream is not reduced as much as in the case of audio stream.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.880-883
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• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.31-39
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• 1998

This paper presents the design and implementation of a new multimedia fixed-point DSP (MDSP) core for portable multimedia applications. The MDSP instruction set is designed through the analysis of multimedia algorithms and DSP instruction sets. The MDSP architecture employs parallel processing techniques, such as SIMD and vector processing as well as DSP techniques. The instruction set can handle various data formats and MDSP can perform two MAC operations in parallel. The switching network and packing network can increase the performance by overlapping data rearrangement cycles with computation cycles. We have designed Verilog HDL models and the 0.6 $\mu\textrm{m}$ Samsung KG75000 SOG library is used. The total gate count is 68,831 and the clock frequency is 30 MHz.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.839-842
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• 1998

The wide spread of multimedia system demands a large viewin gdesply device which can inform a message to many peoples in open area. This paper is about the design, simulating and testing of a large viewing LED pannel control ASIC(application specific integrated circuit). This LED pannel control ASIC runs on 16 bit microprocessor MC68EC000 and has following functions:16 line interlaced LED pannel controller, memory controller, 16 channel priority inerrupt controller, 2 channel direct memory access controller, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16byte FIFO, IBM PC/AT compatible keyboard interface, battery backuped real time clock, ISA bus controller, battery backuped 256 byte SRAM and watech dog timer. The 0.6micron CMOS sea of gate is used to design the ASIC in amount of about 39,000 gates.