• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.10
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• pp.539-545
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• 2004

In this paper, we consider the problem of capacitance matrix calculation for strip-line and other interconnects crossings. The problem is formulated in the spectral domain using the method of moments. Sinc-functions are employed as basis functions. Conventionally, such a formulation leads to a large, non-sparse system of linear equations in which the calculation of each of the coefficient requires the evaluation of a Fourier-Bessel integral. Such calculations are computationally very intensive. In the method proposed here, we provide simplified expressions for the coefficients in the moment method matrix. Using these simplified expressions, the coefficients can be calculated very efficiently. This leads to a fast evaluation of the capacitance matrix of the structure. Computer simulations are provided illustrating the validity of the method proposed.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.23-29
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• 2014

Less power consumption, lower cost, smaller size and more functionality are the increasing demands for consumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet this requirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. This study discribe the thermal stress reliability trend for successful implementation of 3-D packaging.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.93-100
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• 2003

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies. These latter technologies have not kept pace with the IC scaling trends, resulting in a so-called“interconnect technology gap”. Multilayer thin film technology is proposed as a“bridge”- technology between the very high density IC technology and the coarse standard PCB technology. It is also a key enabling technology for the realisation of true“System-in-a-Package”(SIP) solutions, combining multiple“System-on-a-Chip”(SOC) IC's with other components and also integrating passive components in its layers. A further step is to use this technology to realise new functionalities on top of active wafers. These additional“above-IC”processed layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.99-104
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• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.1
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• pp.39-46
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• 2021

The quantitative measurement of interfacial adhesion energy (Gc) of multilayer thin films for Cu interconnects was investigated using a double cantilever beam (DCB) and 4-point bending (4-PB) test. In the case of a sample with Ta diffusion barrier applied, all Gc values measured by the DCB and 4-PB tests were higher than 5 J/㎡, which is the minimum criterion for Cu/low-k integration without delamination. However, in the case of the Ta/Cu sample, measured Gc value of the DCB test was lower than 5 J/㎡. All Gc values measured by the 4-PB test were higher than those of the DCB test. Measured Gc values increase with increasing phase angle, that is, 4-PB test higher than DCB test due to increasing plastic energy dissipation and roughness-related shielding effects, which matches well interfacial fracture mechanics theory. As a result of the 4-PB test, Ta/Cu and Cu/Ta interfaces measured Gc values were higher than 5 J/㎡, suggesting that Ta is considered to be applicable as a diffusion barrier and a capping layer for Cu interconnects. The 4-PB test method is recommended for quantitative adhesion energy measurement of the Cu interconnect interface because the thermal stress due to the difference in coefficient of thermal expansion and the delamination due to chemical mechanical polishing have a large effect of the mixing mode including shear stress.