• Journal of Information Processing Systems
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• v.7 no.3
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• pp.435-446
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• 2011

Microprocessors are becoming increasingly vulnerable to soft errors due to the current trends of semiconductor technology scaling. Traditional redundant multi-threading architectures provide perfect fault tolerance by re-executing all the computations. However, such a full re-execution technique significantly increases the verification workload on the processor resources, resulting in severe performance degradation. This paper presents a pro-active verification management approach to mitigate the verification workload to increase its performance with a minimal effect on overall reliability. An anomaly-speculation-based filter checker is proposed to guide a verification priority before the re-execution process starts. This technique is accomplished by exploiting a value similarity property, which is defined by a frequent occurrence of partially identical values. Based on the biased distribution of similarity distance measure, this paper investigates further application to exploit similar values for soft error tolerance with anomaly speculation. Extensive measurements prove that the majority of instructions produce values, which are different from the previous result value, only in a few bits. Experimental results show that the proposed scheme accelerates the processor to be 180% faster than traditional fully-fault-tolerant processor with a minimal impact on overall soft error rate.

• Journal of Digital Convergence
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• v.12 no.6
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• pp.349-354
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• 2014

A maze-escaping method with cooperating work of robots alongside one another will be proposed in this paper. Educational robots can communicate each other using Zigbee; however, they can't solve problems together due to their lack of arithmetic function. The robots walk upright controlled by a motion program; furthermore, they recognize an intersection or a dead-end in the use of distant sensors with sending data and receiving commands from the central control system. The maze-search algorithms were modified so that all robots can effectively navigate the maze.

• Electronics and Telecommunications Trends
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• v.13 no.3 s.51
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• pp.61-70
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• 1998

The obvious way to make a computer system more powerful is to make the processor as fast as possible. Furthermore, adopting a large number of such fast processors would be the next step. This multiprocessor system could be useful only if it distributes workload uniformly and if its processors are fully utilized. To achieve a higher processor utilization, memory access latency must be reduced as much as possible and even more the remaining latency must be hidden. The actual latency can be reduced by using fast logic and the effective latency can be reduced by using cache. This article discusses what the memory latency problem is, how serious it is by presenting analytical and simulation results, and existing techniques for coping with it; such as write-buffer, relaxed consistency model, multi-threading, data locality optimization, data forwarding, and data prefetching.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.4
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• pp.242-250
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• 2007

Wireless sensor networks are subject to highly heterogeneous system requirements in terms of their functionality and performance due to their broad application areas. Though the heterogeneity hinders the opportunity of developing a single universal platform for sensor networks, efforts to provide uniform, inter-operable and scalable ones for sensor networks are still essential for the growth of the industry as well as their technological advance. As a part of our work to develop such a robust platform, this paper presents the software architecture for sensor nodes with focus on our sensor node operating system and its configuration methodology. Addressing principle issues in its design space which includes programming, execution, task scheduling and software layer models, our architecture is highly reconfigurable with respect to system resources and functional requirements and also highly efficient in supporting multi-threading under small system resources.

• Journal of Institute of Control, Robotics and Systems
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• v.16 no.1
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• pp.90-95
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• 2010

This paper describes the development of integrated head and eye tracker system. Vision based head tracker is performed and it has 7mm error in 300mm translation. The epi-polar method and point matching are used for determining a position of head and rotational degree. High brightness LEDs are installed on helmet and the installed pattern is very important to match the points of stereo system. Eye tracker also uses LED for constant illumination. A Position of gazed object(3m distance) is determined by pupil tracking and eye tracker has 1~5 pixel error. Integration of result data of each tracking system is important. RS-232C communication is applied to integrated system and triggering signal is used for synchronization.

• Proceedings of the Korean Society of Computer Information Conference
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• 2012.07a
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• pp.297-300
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• 2012

현재 cache의 성능 향상을 위한 많은 기법들이 제안되고 있으며, Latency Hiding 기법 역시 cache의 효율적인 사용을 위해 많은 연구가 진행 되어 왔다. write buffer를 사용한 write Latency hiding기법이나 multi threading을 사용한 Latency Hiding 방법 등 여러 기법들이 연구되어 왔으며, 지금도 Latency hiding을 위한 많은 연구들이 지속적으로 진행되고 있다. 본 논문 역시 효율적인 Latency Hiding을 위한 누적 버퍼를 제안한다. 본 논문은 누적 버퍼의 활용도를 조사하여 얼마나 효율적으로 Latency를 은폐했는지, 또 버퍼를 사용함으로써 얻는 다른 이점에 대해 집중적으로 연구하였다.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.19-24
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• 2011

As era of multi-core processors has arrived, transactional memory has been considered as an effective method to achieve easy and fast multi-threaded programming. Various hardware transactional memory systems such as UTM, VTM, FastTM, LogTM, and LogTM-SE, have been introduced in order to implement high-performance multi-core processors. Especially, LogTM-SE has provided study performance with an efficient memory management policy and a practical thread scheduling method through conflict detection based on signatures. However, increasing number of cores on a processor imposes the hardware complexity for signature processing. This causes overall performance degradation due to the heavy workload on signature comparison. In this paper, we propose a new architecture of multiple signature comparison to improve conflict detection of signature based transactional memory systems.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.1
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• pp.72-79
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• 2011

The importance of parallel programming seriously emerges ever since the modern microprocessor architecture has been shifted to the multi-core system. Transactional Memory has been proposed to address synchronization which is usually implemented by using locks. However, the lock based synchronization method reduces the parallelism and has the possibility of causing deadlock. In this paper, we propose an efficient method to utilize transactional memory for the situation which has high contention. The proposed idea is based on the theoretical analysis and it is verified with simulation results. The simulation environment has been implemented using HTM(Hardware Transactional Memory) systems. We also propose a model of the dining philosopher problem to discuss the efficient resource management using the transactional memory technique.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.1
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• pp.453-458
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• 2016

One of the most common applications of machine vision is quality inspections in automated production. In this study, a welding inspection system that is controlled by a PC and a PLC equipped with a multi-camera setup was developed. The system was designed to measure the primary dimensions, such as the length and width of the welding areas. The TCP/IP protocols and multi-threading techniques were used for parallel control of the optical components and physical distribution. A coaxial light was used to maintain uniform lighting conditions and enhance the image quality of the weld areas. The core image processing system was established through a combination of various algorithms from the OpenCV library. The proposed vision inspection system was fully validated for an actual weld production line and was shown to satisfy the functional and performance requirements.

• Korean Journal of Remote Sensing
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• v.13 no.1
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• pp.13-30
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• 1997

Recent improvements of satellite remote sensing sensors which are represented by hyperspectral imaging sensors and high spatial resolution sensors provide a large amount of data, typically several hundred megabytes per one scene. Moreover, increasing information exchange via internet and information super-highway requires the developments of more active service systems for processing and analysing of remote sensing data in order to provide value-added products. In this sense, an advanced satellite data processing system is being developed to achive high performance in computing speed and efficieney in processing a huge volume of data, and to make possible network computing and easy improving, upgrading and managing of systems. JAVA internet programming language provides several advantages for developing software such as object-oriented programming, multi-threading and robust memory managent. Using these features, a satellite data processing system named as GeoPixel has been developing using JAVA language. The GeoPixel adopted newly developed techniques including object-pipe connect method between each process and multi-threading structure. In other words, this system has characteristics such as independent operating platform and efficient data processing by handling a huge volume of remote sensing data with robustness. In the evaluation of data processing capability, the satisfactory results were shown in utilizing computer resources(CPU and Memory) and processing speeds.