• Journal of Ocean Engineering and Technology
• /
• v.36 no.3
• /
• pp.181-193
• /
• 2022

This study presents a mission management technique that is a key component of underwater docking system used to expand the operating range of autonomous underwater vehicle (AUV). We analyzed the docking scenario and AUV operating environment, defining the feasible initial area (FIA) level, event level, and global path (GP) command to improve the rate of docking success and AUV safety. Non-holonomic constraints, mounted sensor characteristic, AUV and mission state, and AUV behavior were considered. Using AUV and docking station, we conducted experiments on land and at sea. The first test was conducted on land to prevent loss and damage of the AUV and verify stability and interconnection with other algorithms; it performed well in normal and abnormal situations. Subsequently, we attempted to dock under the sea and verified its performance; it also worked well in a sea environment. In this study, we presented the mission management technique and showed its performance. We demonstrated AUV docking with this algorithm and verified that the rate of docking success was higher compared to those obtained in other studies.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.431-432
• /
• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.05d
• /
• pp.109-112
• /
• 2003

Recently, CMP (Chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. Also, we have collected the silica abrasive powders by filtering after subsequent CMP process for the purpose of abrasive particle recycling. And then, we annealed the collected abrasive powders to promote the mechanical strength of reduced abrasion force. Finally, we compared the CMP characteristics between self-developed KOH-based silica abrasive slurry and original slurry. As our experimental results, we obtained the comparable removal rate and good planarity with commercial products. Consequently, we can expect the saving of high cost slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.380-381
• /
• 2006

Chemical mechanical polishing (CMP) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, the cost of ownership and cost of consumables are relatively high because of expensive slurry. In this paper, we studied the mixed abrasive slurry (MAS). In order to save the costs of slurry, the original silica slurry was diluted by de-ionized water (DIW). And then, $ZrO_2$, $CeO_2$, and $MnO_2$ abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry. We have also investigate the possibility of mixed abrasive slurry for the oxide CMP application.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.18 no.6
• /
• pp.515-520
• /
• 2005

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. Also CMP process got into key process for global planarization in the chip manufacturing process. In this study, potentiodynamic polarization was carried out to investigate the influences of $H_2O_2$ concentration and metal oxide formation through the passivation on tungsten and titanium. Fortunately, the electrochemical behaviors of tungsten and titanium are similar, an one may expect. As an experimental result, electrochemical corrosion of the $5\;vol\%\;H_2O_2$ concentration of tungsten and titanium films was higher than the other concentrations. According to the analysis, the oxidation state and microstructure of surface layer were strongly influenced by different oxidizer concentration. Moreover, the oxidation kinetics and resulting chemical state of oxide layer played critical roles in determining the overall CMP performance. Therefore, we conclude that the CMP characteristics tungsten and titanium metal layer including surface roughness were strongly dependent on the amounts of hydrogen peroxide oxidizer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.11a
• /
• pp.39-42
• /
• 2002

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of reused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity(WIWNU) were measured as a function of different slurry composition. As a experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt% contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows In the first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saving of high costs of slurry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.9
• /
• pp.759-764
• /
• 2003

Recently, CMP (chemical mechanical polishing) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, COO (cost of ownership) and COC (cost of consumables) were relatively increased because of expensive slurry. In this paper, we have studied the possibility of recycle of roused silica slurry in order to reduce the costs of CMP slurry. The post-CMP thickness and within-wafer non-uniformity (WIWNU) wore measured as a function of different slurry composition. As an experimental result, the performance of reused slurry with annealed silica abrasive of 2 wt％ contents was showed high removal rate and low non-uniformity. Therefore, we propose two-step CMP process as follows , In tile first-step CMP, we can polish the thick and rough film surface using remaked slurry, and then, in the second-step CMP, we can polish the thin film and fine pattern using original slurry. In summary, we can expect the saying of high costs of slurry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.4
• /
• pp.378-383
• /
• 2004

Tungsten is widely used as a plug for the multi-level interconnection structures. However, due to the poor adhesive properties of tungsten(W) on SiO$_2$ layer, the Ti/TiN barrier layer is usually deposited onto SiO$_2$ for increasing adhesion ability with W film. Generally, for the W-CMP(chemical mechanical polishing) process, the passivation layer on the tungsten surface during CMP plays an important role. In this paper, the effect of oxidant on the polishing selectivity of W/Ti/TiN layer was investigated. The alumina(A1$_2$O$_3$)-based slurry with $H_2O$$_2$ as the oxidizer was used for CMP applications. As an experimental result, for the case of 5 wt％ oxidizer added, the removal rates were improved and polishing selectivity of 1.4:1 was obtained. It was also found that the CMP characteristics of W and Ti metal layer including surface roughness were strongly dependent on the amounts of $H_2O$$_2$ oxidizer.

• Journal of the Korea Society for Simulation
• /
• v.25 no.4
• /
• pp.43-52
• /
• 2016

Wireless sensor network (WSN) technology has been implemented using commercial off-the-shelf microcontrollers (MCUs), In this paper, we propose a simulation environment to realize the physical evaluation of FPGA-based node by considering vertically cross-layered WSN in terms of physical node device and network interconnection perspective. The proposed simulation framework emulates the physical FPGA-based sensor nodes to interoperate with the NS3 through the runtime infrastructure (RTI). For the emulation and interoperation of FPGA-based nodes, we extend a vendor-providing FPGA design tool from the host computer and a script to execute the interoperation procedures. The standalone NS-3 is also revised to perform interoperation through the RTI. To resolve the different time-advance mechanisms between the FPGA emulation and event-driven NS3 simulation, the pre-simulation technique is applied to the proposed environment. The proposed environment is applied to IEEE 802.15.4-based low-rate, wireless personal area network communication.

• Journal of the Microelectronics and Packaging Society
• /
• v.24 no.2
• /
• pp.11-15
• /
• 2017

As the heat dissipation problem is increased in 3D multi flip chip packages, an improvement of thermal conductivity in bonding interfaces is required. In this study, the effect of alumina filler addition was investigated in non-conductive paste(NCP). The fine alumina filler having average particles size of 400 nm for the fine pitch interconnection was used. As the alumina filler content was increased from 0 to 60 wt%, the thermal conductivity of the cured product was increased up to 0.654 W/mK at 60 wt%. It was higher value than 0.501 W/mK which was reported for the same amount of silica. It was also found out that the addition of fine sized alumina filler resulted in the smaller decrease in thermal conductivity than the larger sized particles. The viscosity of NCP with alumina addition was increased sharply at the level of 40 wt%. It was due to the increase of the interaction between the filler particles according to the finer particle size. In order to achieve the appropriate viscosity and excellent thermal conductivity with fine alumina fillers, the highly efficient dispersion process was considered to be important.