• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.

• Journal of KIISE
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• v.42 no.2
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• pp.177-182
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• 2015

The era of multi-core processors has begun since the limit of the clock speed has been reached. These days, multi-core technology is used not only in desktops, servers, and table PCs, but also in smartphones. In this architecture, there is always interference between processes, because of the sharing of system resources. To address this problem, cache partitioning is used, which can be roughly divided into two types: software and hardware cache partitioning. When it comes to dynamic cache partitioning, hardware cache partitioning is superior to software cache partitioning, because it needs no page copy. In this paper, we compare the effectiveness of hardware and software cache partitioning on the AMD Opteron 6282 SE, which is the only commodity processor providing hardware cache partitioning, to see whether this technique can be effectively deployed in dynamic environments.

• ETRI Journal
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• v.43 no.3
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• pp.524-537
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• 2021

High-performance Linpack (HPL) is among the most popular benchmarks for evaluating the capabilities of computing systems and has been used as a standard to compare the performance of computing systems since the early 1980s. In the initial system-design stage, it is critical to estimate the capabilities of a system quickly and accurately. However, the original HPL mathematical model based on a single core and single communication layer yields varying accuracy for modern processors and accelerators comprising large numbers of cores. To reduce the performance-estimation gap between the HPL model and an actual system, we propose a mathematical model for multi-communication layered HPL. The effectiveness of the proposed model is evaluated by applying it to a GPU cluster and well-known systems. The results reveal performance differences of 1.1% on a single GPU. The GPU cluster and well-known large system show 5.5% and 4.1% differences on average, respectively. Compared to the original HPL model, the proposed multi-communication layered HPL model provides performance estimates within a few seconds and a smaller error range from the processor/accelerator level to the large system level.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.31-39
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• 2013

In this paper, we propose a power-efficient scheduling scheme that stochastically minimizes the power consumption of a real-time parallel task while meeting the deadline on multicore processors. The proposed scheme applies the parallel processing that executes a task on multiple cores concurrently, and activates a part of all available cores with unused cores powered off, in order to save power consumption. It is proved that the proposed scheme minimizes the mean power consumption of a real-time parallel task with probabilistic computation amount on DVFS-enabled multicore processors with a finite set of discrete clock frequencies. Evaluation shows that the proposed scheme saves up to 81% power consumption of the previous method.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.2
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• pp.542-558
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• 2023

A digital focus index (DFI) is a value used to determine image focus in scientific apparatus and smart devices. Automatic focus (AF) is an iterative and time-consuming procedure; however, its processing time can be reduced using a general processing unit (GPU) and a multi-core processor (MCP). In this study, parallel architectures of a minimax search algorithm (MSA) are applied to two DFIs: range algorithm (RA) and image contrast (CT). The DFIs are based on a histogram; however, the parallel computation of the histogram is conventionally inefficient because of the bank conflict in shared memory. The parallel architectures of RA and CT are constructed using parallel reduction for MSA, which is performed through parallel relative rating of the image pixel pairs and halved the rating in every step. The array size is then decreased to one, and the minimax is determined at the final reduction. Kernels for the architectures are constructed using open source software to make it relatively platform independent. The kernels are tested in a hexa-core PC and an embedded device using Lenna images of various sizes based on the resolutions of industrial cameras. The performance of the kernels for the DFIs was investigated in terms of processing speed and computational acceleration; the maximum acceleration was 32.6× in the best case and the MCP exhibited a higher performance.

• Journal of the Korea Society of Computer and Information
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• v.16 no.8
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• pp.119-128
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• 2011

This paper introduces design space exploration of many-core processors that meet high performance and low power required by the beamforming algorithm of image signals of mobile ultrasound. For the design space exploration of the many-core processor, we mapped different number of ultrasound image data to each processing element of many-core, and then determined an optimal many-core processor architecture in terms of execution time, energy efficiency and area efficiency. Experimental results indicate that PE=4096 and 1024 provide the highest energy efficiency and area efficiency, respectively. In addition, PE=4096 achieves 46x and 10x better than TI DSP C6416, which is widely used for ultrasound image devices, in terms of energy efficiency and area efficiency, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06c
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• pp.134-138
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• 2007

점차 더 벌어지는 CPU 속도와 메모리 속도의 차이로 인하여 메모리 접근 병목 현상이 발생하였고, 이 현상을 극복하기 위하여 캐시를 고려한 인덱스 구조에 관한 연구가 계속 되었다. 또한 최근 CPU 트렌드가 싱글 코어에서 멀티 코어로 전환점을 맞으면서 캐시메모리의 효율에 대한 중요성이 더욱 부각되었다. 본 논문은 최신 프로세서를 탑재한 시스템에서 메인 메모리 데이터베이스 시스템을 위한 인덱스 구조들의 성능을 비교 평가하고, 그 중 캐시를 고려한 트리 인덱스의 성능이 유용함을 보인다.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.175-183
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• 2016

This paper brings out a novel method for reducing Near end and Far end Crosstalk using Electromagnetic Band Gap structures (EBG) in High Speed RF transmission lines. This work becomes useful in high speed closely spaced Printed Circuit Board (PCB) traces connected to multi core processors. By using this method, reduction of −40dB in Near-End Crosstalk (NEXT) and −60 dB in Far End Crosstalk (FEXT) is achieved. The results are validated through experimental measurements. Time domain analysis is performed to validate the signal integrity property of coupled transmission lines.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.747-748
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• 2008

In this paper, we propose a new algorithm for task scheduling consisting of subtask partitioning and subtask priority scheduling steps in order to keep the peak power under the system specification. The subtask partitioning stepis performed to minimize the idle operation time for processors by dividing a task into multiple subtasks using the least square method developed with power consumption pattern of tasks. In the subtask priority scheduling step, a priority is assigned to a subtask based on the power requirement and the power variation of subtask so that the peak power violation can be minimized and the task can be completed within the execution time deadline.

• Journal of Information Technology Applications and Management
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• v.14 no.4
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• pp.121-138
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• 2007

This study proposes a method to improve network security systems based on critical success factors for systems development. To accomplish the research objective, the study analyzes required functions of network security systems and reviews existing methods to improve network security systems. Based on the analyses and literature review, critical success factors for development of network security systems are identified and a new method to improve network security systems based on the critical success factors is proposed. The proposed method to improve network security systems is based on utilizing multi-core processors. A prototype is developed and validated. This study will provide a good case in the network security area where research incorporating both engineering and management disciplines lacks.