• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• Journal of applied mathematics & informatics
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• v.42 no.2
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• pp.257-281
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• 2024

In real life, a decision-maker can assign multiple values for pairwise comparison with a certain confidence level. Studies incorporating multi-choice parameters in multi-criteria decision-making methods are lacking in the literature. So, In this work, an extension of the Best-Worst Method (BWM) with multi-choice pairwise comparisons and multi-choice confidence parameters has been proposed. This work incorporates an extension to the original BWM with multi-choice uncertainty and confidence level. The BWM presumes the Decision-Maker to be fully confident about preference criteria vectors best to others & others to worst. In the proposed work, we consider uncertainty by giving decision-makers freedom to have multiple choices for preference comparison and having a corresponding confidence degree for each choice. This adds one more parameter corresponding to the degree of confidence of each choice to the already existing MCDM, i.e. multi-choice BWM and yields acceptable results similar to other studies. Also, the consistency ratio remained low within the acceptable range. Two real-life case studies are presented to validate our study on proposed models.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.64-73
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• 1992

This paper presents the design of multi-level logic optimization algorithm and the development of the SMILE system based on the algorithm. Considering the fanin constraints in algorithmic level, SMILE performs global and local optimization in a predefined sequence using heuristic information. Designed under the Sogang Silicon Compiler design environment, SMILE takes the SLIF netlist or Berkeley equation formats obtained from high-level synthesis process, and generates the optimized circuits in the same format. Experimental results show that SMILE produces the promising results for some circuits from MCNC benchmarks, comparable to the popularly used multi-level logic optimization system, MIS.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1318-1328
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• 2015

The photovoltaic (PV) power conditioning system for small-scale applications has gained significant interest in the past few decades. However, the standalone mode of operation has been rarely approached. This paper presents a two-stage multi-level micro-inverter topology that considers the different operation modes. A multi-output flyback converter provides both the DC-Link voltage balancing for the multi-level inverter side and maximum power point tracking control in grid connection mode in the PV stage. A modified H-bridge multi-level inverter topology is included for the AC output stage. The multi-level inverter lowers the total harmonic distortion and overall ratings of the power semiconductor switches. The proposed micro-inverter topology can help to decrease the size and cost of the PV system. Transient analysis and controller design of this micro-inverter have been proposed for stand-alone and grid-connected modes. Finally, the system performance was verified using a 120 W hardware prototype.

• Proceedings of the KIPE Conference
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• 2002.11a
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• pp.171-174
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• 2002

This paper deals with a novel method in order to analyze the harmonic characteristics in the multi-level inverter. Generally, the magnitude of harmonic components is different according to the carrier PWM techniques, modulation Index(Mi), and the level of multi-level inverter The previous papers analyzed the harmonic characteristics from the viewpoint of the space vector. Hence, the calculation of the harmonic vector becomes difficult and complex in 4-level or more than S-level. However, the proposed method of this paper reduced an amount of calculation and simplified the process of calculation by using the relationship between reference voltage and output phase voltage to load neutral. This paper analyzed the harmonic and it is applied to the multi-carrier PWM techniques in 5- level and other-level of cascaded inverter system.

• Journal of Power Electronics
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• v.13 no.2
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• pp.296-303
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• 2013

This paper proposes a high efficiency three-phase cascaded phase shifted H-bridge multi-level inverter without DC/DC converters for grid-tied multi string photovoltaic (PV) applications. The cascaded H-bridge topology is suitable for PV applications since each PV module can act as a separate DC source for each cascaded H-bridge module. The proposed phase shifted H-bridge multi-level topology offers advantages such as operation at a lower switching frequency and a lower current ripple when compared to conventional two level topologies. It is also shown that low ripple sinusoidal current waveforms are generated with a unity power factor. The control algorithm permits the independent control of each DC link voltage with a maximum power point for each string of PV modules. The use of the controller area network (CAN) communication protocol for H-bridge multi-level inverters, along with localized PWM generation and PV voltage regulation are implemented. It is also shown that the expansion and modularization capabilities of the H-bridge modules are improved since the individual inverter modules operate more independently. The proposed topology is implemented for a three phase 240kW multi-level PV power conditioning system (PCS) which has 40kW H-bridge modules. The experimental results show that the proposed topology has good performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.9C
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• pp.880-886
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• 2009

Recently, the memory is used in many electronic devices, thus, the many researchers make a study of the memory. To increase a storage capacity per memory block, the researchers study for reducing the fabrication process of memory and multi-level cell memory which is storing more than 2-bits in a cell. However, the multi-level cell memory has low bit-error rates by various noises. In this paper, we study the noise of multi-level cell memory, and we propose the channel model of multi-level cell memory.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.3
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• pp.234-240
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• 2007

In this paper, a novel multi-level inverter for low cost high speed switched reluctance(SR) drive is proposed. The proposed multi-level converter has reduced number of power switches and diodes than that of a conventional asymmetric converter for SRM and smaller voltage rating of the dump capacitor comparing with energy efficient c-dump converter. It can supply five operating modes that is boosted, DC-link, zero, negative bias and negative boosted voltage. The proposed multi-level converter has fast excitation and demagnetization modes of phase current, so dynamic response can be achieved. The proposed multi-level converter is verified by computer simulation and experimental results.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.1
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• pp.26-32
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• 2009

The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit sequentiality in accesses common for such systems and hide the increasing relative cost of disk I/O, existing multi-level storage studies have focused mostly on cache replacement strategies. In this paper, we show that prefetching algorithms designed for single-level systems may have their limitations magnified when applied to multi-level systems. Overly conservative prefetching will not be able to effectively use the lower-level cache space, while overly aggressive prefetching will be compounded across levels and generate large amounts of wasted prefetch. We design and implement a hierarchy-aware lower-level prefetching strategy called PMS(Prefetching strategy for Multi-level Storage system) that applicable to any upper level prefetching algorithms. PMS does not require any application hints, a priori knowledge from the application or modification to the va interface. Instead, it monitors the upper-level access patterns as well as the lower-level cache status, and dynamically adjusts the aggressiveness of the lower-level prefetching activities. We evaluated the PMS through extensive simulation studies using a verified multi-level storage simulator, an accurate disk simulator, and access traces with different access patterns. Our results indicate that PMS dynamically controls aggressiveness of lower-level prefetching in reaction to multiple system and workload parameters, improving the overall system performance in all 32 test cases. Working with four well-known existing prefetching algorithms adopted in real systems, PMS obtains an improvement of up to 35% for the average request response time, with an average improvement of 16.56% over all cases.

• Annual Conference on Human and Language Technology
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• 2018.10a
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• pp.259-262
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• 2018

기계독해의 목표는 기계가 주어진 문맥을 이해하고 문맥에 대한 질문에 대답할 수 있도록 하는 것이다. 본 논문에서는 Multi-level Attention에 정보를 효율적으로 융합 수 있는 Fusion 함수를 결합하고, Answer module에Stochastic multi-step answer를 적용하여 SQuAD dev 데이터 셋에서 EM=78.63%, F1=86.36%의 성능을 보였다.