• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• Journal of the Korea Computer Industry Society
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• v.5 no.1
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• pp.147-156
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• 2004

In this paper, a new fast motion estimation algorithm which is based on the Block Sum Pyramid Algorithm(BSPA) is presented. The Spiral Diamond Mesh Search scheme and Partial Distortion Elimination scheme of Efficient Multi-level Successive Elimination Algorithm were improved and then the improved schemes were applied to the BSPA. The motion estimation accuracy of the proposed algorithm is nearly 100% and the cost of Block Sum Pyramid Algorithm was reduced in the proposed algorithm. The efficiency of the proposed algorithm was verified by experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.12C
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• pp.1232-1239
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• 2006

In video standards such as MPEG-1/2/4 and H.264/AVC, motion estimation / compensation(ME/MC) process causes the most encoding complexity of video encoder. The full search method, which is used in general video codecs, exhausts much encoding time because it compares current macroblock with those at all positions within search window for searching a matched block. For the alleviation of this problem, the fast search methods such as TSS, NTSS, DS and HEXBS are exploited at first. Thereafter, DS based MVFAST, PMVFAST, MAS and FAME, which utilize temporal or spacial correlation characteristics of motion vectors, are developed. But there remain the problems of image quality degradation and algorithm complexity increase. In this thesis, the proposed algorithm maximizes search speed and minimizes the degradation of image quality by determining initial search point correctly and using simple one-dimension search patterns considering motion characteristics of each frame.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.730-737
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• 2013

In this paper, Constrained One-Bit Transform (C1BT) based motion estimation using extension of matching error criterion is proposed. C1BT based motion estimation algorithm exploiting Number of Non-Matching Points (NNMP) instead of Sum of Absolute Differences (SAD) that used in the Full Search Algorithm (FSA) facilitates hardware implementation and significantly reduces computational complexity. However, the accuracy of motion estimation is decreased. To improve inaccurate motion estimation, this algorithm based motion estimation extending matching error criterion of C1BT is proposed in this paper. Experimental results show that proposed algorithm has better performance compared with the conventional algorithm in terms of Peak-Signal-to-Noise-Ratio (PSNR).

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.4 s.310
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• pp.55-65
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• 2006

Most of fast block motion estimation algorithms reported so far in literatures aim to reduce the computation in terms of the number of search points, thus do not fit well with multimedia processors due to their irregular data flow. For multimedia processors, proper reuse of data is more important than reducing number of absolute difference operations because the execution cycle performance strongly depends on the number of off-chip memory access. Therefore, in this paper, we propose a Hexagon-shape line search (HEXSLS) algorithm using line search pattern which can increase data reuse from on-chip local buffer, and check sub-sampling points in line search pattern to reduce unnecessary SAD operation. Our experimental results show that the prediction error (MAE) performance of the proposed HEXSLS is similar to that of the full search block matching algorithm (FSBMA), while compared with the hexagon-based search (HEXBS), the HEXSLS outperforms. Also the proposed HEXSLS requires much lesser off-chip memory access than the conventional fast motion estimation algorithm such as the hexagon-based search (HEXBS) and the predictive line search (PLS). As a result, the proposed HEXSLS algorithm requires smaller number of execution cycles on media processor.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.885-888
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• 2000

Among the previous searching methods, there are the typical methods such as full search and three-step search, etc. Block motion estimation using exhaustive search is too computationally intensive. To apply in practice, recently proposed fast algorithms have been focused on reducing the computational complexity by limiting the number of searching points. According to the reduction of searching points, the quality performance is aggravated in those algorithms. In this paper, We present a fast and efficient search algorithm for block motion estimation that produces better quality performance and less computational time compared with a three-step search (TSS). Previously the proposed Two Step Search Algorithm (TWSS) by Fang-Hsuan Cheng and San-Nan sun is based on the ideas of dithering pattern for pixel decimation using a part of a block pixels for BMA (Block Matching Algorithm) and multi-candidate to compensate quality performance with several locations. This method has good quality performance at slow moving images, but has bad quality performance at fast moving images. To resolve this problem, the proposed algorithm in this paper considers spatial and temporal correlation using neighbor and previous blocks to improve quality performance. This performance uses neighbor motion vectors and previous motion vectors in addition, thus it needs more searching points. To compensate this weakness, the proposed algorithm uses statistical character of dithering matrix. The proposed algorithm is superior to TWSS in quality performance and has similar computational complexity

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1080-1087
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• 2005

Significant computations for full search (FS) motion estimation have been a big obstacle in real-time video coding and recent MPEG-4 AVC (advanced video coding) standard requires much more computations than conventional MPEG-2 for motion estimation. To reduce an amount of computation of full search (FS) algorithm for fast motion estimation, we propose a new and fast matching algorithm without any degradation of predicted images like the conventional FS. The computational reduction without any degradation in predicted image comes from fast elimination of impossible candidate motion vectors. We obtain faster elimination of inappropriate motion vectors using efficient matching units from localization of complex area in image data and dithering order based matching scan. Our algorithm reduces about $30\%$ of computations for block matching error compared with the conventional partial distortion elimination (PDE) algorithm, and our algorithm will be useful in real-time video coding applications using MPEG-4 AVC or MPEG-2.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.78-84
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• 2009

In general video coding systems, motion estimation (ME) is regarded as a vital component in a video coder as it consumes a large amount of computation resources. Fractional pixel motion estimation can improve the video compression rate at the cost of higher computational complexity. It is based on the experimental results that the sum of absolute differences (SAD) shows parabolic shape and thus can be approximated by using interpolation technique. In this paper, we propose a fast fractional pixel search algorithm by combining SASR (Simplified Adaptive Search Range) and the CBCDS (Center Biased Cross-Diamond Search) pattern with the predicted motion vector. Compare with the fractional pel full search and the CBFPS, the proposed CBCDS algorithms can reduce fractional pel search points up to 81.4%, respectively with the PSNR lost about 0.05dB.

• The KIPS Transactions:PartB
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• v.11B no.3
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• pp.309-316
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• 2004

In this paper, we proposed the TDS(T-shape Diamond Search) based on the directions of above, below, left and right points to estimate the motion vector fast and more correctly in this method, we exploit the facts that most motion vectors are enclosed in a circular region with a radius of 2 fixels around search center(0,0). At first, the 4 points in the above, below, left and right around the search center is calculated to decide the point of the MBD(Minimum Block Distortion). And then w. above point of the MBD is checked to calculate the SAD. If the SAD of the above point is less than the previous MBD, this process is repeated. Otherwise, the right and left points of MBD are calculated to decide The points that have the MBD between right point and left point. Above processes are repeated to the predicted direction for motion estimation. Especially, if the motions of image are concentrated in the crossing directions, the points of other directions are omitted. As a result, we can estimate motion vectors fast. Experiments show that the speedup improvement of the proposed algorithm over Diamond Search algorithm(DS) and HEXgon Based Search(HEXBS) can be up to 38∼50％ while maintaining similar image Quality.

• The Journal of the Korea Contents Association
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• v.3 no.2
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• pp.11-18
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• 2003

In this paper, we propose a fast variable block matching algorithm for motion estimation based on bit-patterns. Motion estimation in the proposed algorithm is peformed after the representation of image sequence is transformed 8-bit pixel values into 1-bit ones by the mean pixel value of search block, which brings a short searching time by reducing the computational complexity. Moreover, adaptive searching methods according to the motion information of the block make the procedure of motion estimation efficient by eliminating unnecessary searching processes of low motion block and deepening a searching procedure in high motion block. Experimental results show that the proposed algorithm provides bettor performance - average 0.5dB PSNR improvement and about 99% savings in the number of operations - than full search Hock matching algorithm with a fixed block size.