• Journal of Power Electronics
• /
• v.17 no.1
• /
• pp.242-252
• /
• 2017

This paper deals with the blocking of DC-fault current during DC cable short-circuit conditions in HVDC (High-Voltage DC) transmission systems utilizing Modular Multilevel Converters (MMCs), where a new SubModule (SM) topology circuit for the MMC is proposed. In this SM circuit, an additional Insulated-Gate Bipolar Translator (IGBT) is required to be connected at the output terminal of a conventional SM with a half-bridge structure, hereafter referred to as HBSM, where the anti-parallel diodes of additional IGBTs are used to block current from the grid to the DC-link side. Compared with the existing MMCs based on full-bridge (FB) SMs, the hybrid topologies of HBSM and FBSM, and the clamp-double SMs, the proposed topology offers a lower cost and lower power loss while the fault current blocking capability in the DC short-circuit conditions is still provided. The effectiveness of the proposed topology has been validated by simulation results obtained from a 300-kV 300-MW HVDC transmission system and experimental results from a down-scaled HVDC system in the laboratory.

• Bulletin of the Korean Mathematical Society
• /
• v.31 no.2
• /
• pp.237-242
• /
• 1994

One of the most well-known geometric lattices is a partition lattice. Every upper interval of a partition lattice is a partition lattice. The whitney numbers of a partition lattices are the Stirling numbers, and the characteristic polynomial is a falling factorial. The set of partitions with a single non-trivial block containing a fixed element is a Boolean sublattice of modular elements, so the partition lattice is supersolvable in the sense of Stanley [6]. In this paper, we rephrase four results due to Heller[1] and Murty [4] in terms of matroids and give several characterizations of partition lattices. Our notation and terminology follow those in [8,9]. To clarify our terminology, let G, be a finte geometric lattice. If S is the set of points (or rank-one flats) in G, the lattice structure of G induces the structure of a (combinatorial) geometry, also denoted by G, on S. The size vertical bar G vertical bar of the geometry G is the number of points in G. Let T be subset of S. The deletion of T from G is the geometry on the point set S/T obtained by restricting G to the subset S/T. The contraction G/T of G by T is the geometry induced by the geometric lattice [cl(T), over ^1] on the set S' of all flats in G covering cl(T). (Here, cl(T) is the closure of T, and over ^ 1 is the maximum of the lattice G.) Thus, by definition, the contraction of a geometry is always a geometry. A geometry which can be obtained from G by deletions and contractions is called a minor of G.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.6
• /
• pp.48-55
• /
• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• Journal of the Korea Society for Simulation
• /
• v.11 no.2
• /
• pp.1-16
• /
• 2002

The need for network security is being increasing due to the development of information communication and internet technology. In this paper, firewall models, operating system models and other network component models are constructed. Each model is defined by basic or compound model, referencing DEVS formalism. These models and the simulation environment are implemented with MODSIM III, a general purpose, modular, block-structured high-level programming language which provides direct support for object-oriented programming and discrete-event simulation. In this simulation environment with representative attacks, the following three attacks are generated, SYN flooding and Smurf attack as an attack type of denial of service, Mail bomb attack as an attack type of e-mail. The simulation is performed with the models that exploited various security policies against these attacks. The results of this study show that the modeling method of packet filtering system, proxy system, unix and windows NT operating system. In addition, the results of the simulation show that the analysis of security performance according to various security policies, and the analysis of correlation between availability and confidentiality according to security empowerment.

• Nuclear Engineering and Technology
• /
• v.45 no.4
• /
• pp.439-458
• /
• 2013

REX-10 is a fully-passive small modular reactor in which the coolant flow is driven by natural circulation, the RCS is pressurized by a steam-gas pressurizer, and the decay heat is removed by the PRHRS. To confirm design decisions and analyze the transient responses of an integral PWR such as REX-10, a thermal-hydraulic system code named TAPINS (Thermal-hydraulic Analysis Program for INtegral reactor System) is developed in this study. Based on a one-dimensional four-equation drift-flux model, TAPINS incorporates mathematical models for the core, the helical-coil steam generator, and the steam-gas pressurizer. The system of difference equations derived from the semi-implicit finite-difference scheme is numerically solved by the Newton Block Gauss Seidel (NBGS) method. TAPINS is characterized by applicability to transients with non-equilibrium effects, better prediction of the transient behavior of a pressurizer containing non-condensable gas, and code assessment by using the experimental data from the autonomous integral effect tests in the RTF (REX-10 Test Facility). Details on the hydrodynamic models as well as a part of validation results that reveal the features of TAPINS are presented in this paper.

• Journal of Convergence for Information Technology
• /
• v.9 no.1
• /
• pp.68-73
• /
• 2019

This study is the central axis of the MG (Micro-Grid) configuration and it has the link through the modular hybrid power source and the DC bus, and it provides the function to detect and block the illegal connection by using the standard socket, And to achieve stabilization. Development of power conversion device, smart distribution panel, integrated control system and efficient demand management are required, and compatibility with MG whole system is urgent. This is a hybrid power generation system that is safe with a common power connection protocol and can be easily connected to anyone. This makes it easy to manage data and prepare for expansion of various manufacturers' systems.

• Journal of Engineering Education Research
• /
• v.26 no.1
• /
• pp.37-44
• /
• 2023

Recently, the Internet of Things is attracting attention as an important key technology of the 4th Industrial Revolution, and SW education using physical computing is suggested as a good alternative to supplement the problems raised by beginners in programming education. Among the many teaching tools that can be used for physical computing education, MODI is a modular manufacturing tool that anyone can easily assemble like Lego. MODI is a teaching tool that can improve learners' achievement by linking a self-linked block-type code editor called MODI Studio to lay the foundation for programming in a relatively small amount of time and immediately check the results in person. In this paper, a physical computing education method using MODI was designed to be applied to basic programming courses for programming beginners and applied to after-school classes for middle school students. As a result, it was found that students' interest and satisfaction were much higher in physical computing classes using MODI than in text-based programming classes. It can be seen that physical computing education that allows beginners to see and feel the results in person is more effective than grammar-oriented text programming, and it can have a positive effect on improving basic programming skills by increasing students' participation.

• Journal of the Korea Society of Computer and Information
• /
• v.25 no.10
• /
• pp.261-268
• /
• 2020

In this paper, we propose an effective software education model for youths with disability. This software education model consists of a four-step process. In the first step, it draws the education curriculum of the software education for different types of disabled youths based on the results of comparative analysis of software education field in special education curriculum. In the second step, it suggests achievement standards for effective software education for the disabled students by classifying students with intellectual disabilities and visual, hearing, and physical disabilities without any multiple disabilities. In the third step, the study developed a modular textbook comprised of unplugged activities using coding robot Albert, physical computing, and block/text coding with the reflection of the characteristic of each type of disability. In the fourth step, it applied the textbook to the school field and educated disabled students focusing on experience to allow them to think logically and by stages about different problems they face in daily lives. In addition, by analyzing the results of youths' performance evaluation and surveys, it was shown that 82.3% of developmental disabilities, 78.8% of visual impairments, 90.9% of hearing impairments, and 78.8% of physically disabilities achieved achievements above the "medium" level. These results prove that the software education model for youths with disabilities proposed in this paper is very effective in improving computational chinking of youths with disabilities.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.8
• /
• pp.1741-1748
• /
• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.3
• /
• pp.419-426
• /
• 2021

A high-performance elliptic curve cryptography processor (HP-ECCP) was designed to support five field sizes of 192, 224, 256, 384 and 521 bits over GF(p) defined in NIST FIPS 186-2, and it provides eight modes of arithmetic operations including ECPSM, ECPA, ECPD, MA, MS, MM, MI and MD. In order to make the HP-ECCP resistant to side-channel attacks, a modified left-to-right binary algorithm was used, in which point addition and point doubling operations are uniformly performed regardless of the Hamming weight of private key used for ECPSM. In addition, Karatsuba-Ofman multiplication algorithm (KOMA), Lazy reduction and Nikhilam division algorithms were adopted for designing high-performance modular multiplier that is the core arithmetic block for elliptic curve point operations. The HP-ECCP synthesized using a 180-nm CMOS cell library occupied 620,846 gate equivalents with a clock frequency of 67 MHz, and it was evaluated that an ECPSM with a field size of 256 bits can be computed 2,200 times per second.