• KSII Transactions on Internet and Information Systems (TIIS)
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• v.16 no.4
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• pp.1307-1329
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• 2022

This paper proposes an improved Pseudorandom Sequence Generator (PRSG) based on the concept of modular arithmetic systems with non-integral numbers. The generated random sequence use in various cryptographic applications due to its unpredictability. Here the mathematical model is designed to solve the problem of the non-uniform distribution of the sequences. In addition, PRSG has passed the standard statistical and empirical tests, which shows that the proposed generator has good statistical characteristics. Finally, image encryption has been performed based on the sort-index method and diffusion processing to obtain the encrypted image. After a thorough evaluation of encryption performance, there has been no direct association between the original and encrypted images. The results show that the proposed PRSG has good statistical characteristics and security performance in cryptographic applications.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.813-816
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• 2005

In last several years, the need for the right of privacy and mobile banking has increased. The RSA system is one of the most widely used public key cryptography systems, and its core arithmetic operation IS modular multiplication. P. L. Montgomery proposed a very efficient modular multiplication technique that is well suited to hardware implementation. In this paper, the montgomery modular multiplication algorithms(CIOS, SOS, FIOS) , developed by Cetin Kaya Koc, is presented and implemented using radix-16 and Altera FPGA. Also, we undertake comparisons of power dissipation using Quatrus II PowerPlay Power Analyzer.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.454-460
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• 2003

In this paper, we present a novel method of parallelization of the modular multiplication algorithm to improve time and space complexity on RNS (Residue Number System). The parallel algorithm executes modular reduction using new table lookup based reduction method. MRS (Mixed Radix number System) is used because algebraic comparison is difficult in RNS which has a non-weighted number representation. Conversion from residue number system to certain MRS is relatively fast in residue computer. Therefore magnitude comparison is easily Performed on MRS. By the analysis of the algorithm, it is known that it requires only 1/2 table size than previous approach. And it requires 0(ι) arithmetic operations using 2ㅣ processors.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.9C
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• pp.861-870
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• 2002

In this paper, with targeting on the drawback of RSA of operation speed, a new 1024-bit RSA cryptosystem has been proposed and implemented in hardware to increase the operational speed and perform the variable-length encryption. The proposed cryptosystem mainly consists of the modular exponentiation part and the modular multiplication part. For the modular exponentiation, the RL-binary method, which performs squaring and modular multiplying in parallel, was improved, and then applied. And 4-stage CSA structure and radix-4 booth algorithm were applied to enhance the variable-length operation and reduce the number of partial product in modular multiplication arithmetic. The proposed RSA cryptosystem which can calculate at most 1024 bits at a tittle was mapped into the integrated circuit using the Hynix Phantom Cell Library for Hynix 0.35㎛ 2-Poly 4-Metal CMOS process. Also, the result of software implementation, which had been programmed prior to the hardware research, has been used to verify the operation of the hardware system. The size of the result from the hardware implementation was about 190k gate count and the operational clock frequency was 150㎒. By considering a variable-length of modulus number, the baud rate of the proposed scheme is one and half times faster than the previous works. Therefore, the proposed high speed variable-length RSA cryptosystem should be able to be used in various information security system which requires high speed operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.100-108
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• 2018

This paper describes a design of scalable RSA public-key cryptography processor supporting four key lengths of 512/1,024/2,048/3,072 bits. The modular multiplier that is a core arithmetic block for RSA crypto-system was designed with 32-bit datapath, which is based on the CIOS (Coarsely Integrated Operand Scanning) Montgomery modular multiplication algorithm. The modular exponentiation was implemented by using L-R binary exponentiation algorithm. The scalable RSA crypto-processor was verified by FPGA implementation using Virtex-5 device, and it takes 456,051/3,496347/26,011,947/88,112,770 clock cycles for RSA computation for the key lengths of 512/1,024/2,048/3,072 bits. The RSA crypto-processor synthesized with a $0.18{\mu}m$ CMOS cell library occupies 10,672 gate equivalent (GE) and a memory bank of $6{\times}3,072$ bits. The estimated maximum clock frequency is 147 MHz, and the RSA decryption takes 3.1/23.8/177/599.4 msec for key lengths of 512/1,024/2,048/3,072 bits.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10a
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• pp.646-648
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• 1999

본 논문에서는 RSA 암호 알고리즘의 핵심 계산 과정인 모듈로 곱셈 연산의 효율적인 하드웨어 구현을 위해 새로운 알고리즘과 하드웨어 구조를 제시한다. 기존의 몽고메리 알고리즘이 LSB 우선 방법을 사용한 것과는 달리 여기서는 MSB 우선 방법을 사용하였으며, RSA 암호 시스템에서 키가 일정 기간 동안 변하지 않고 유지된다는 점에 착안해 계수(Modulus)에 대한 보수(Complements)를 미리 계산해 놓고 이를 이용하여 모듈로 감소 처리를 간단히 덧셈으로 치환하도록 하였다. 보수들을 저장할 몇 개의 레지스터와 그들 중 하나를 선택하기 위한 간단한 멀티플렉서(Multiplexer)만을 추가함으로써 몽고메리 알고리즘이 안고 있는 홀수 계수 조건과 사후 연산이라는 번거로움을 없앨 수 있다. 본 논문에서 제안하는 알고리즘은 하드웨어 복잡도가 몽고메리 알고리즘과 비슷하며 그 내부 계산 구조를 보여주는 DG(Dependence Graph)의 지역 연결성 (Local Connection), 모듈성(Modularity), 데이터의 규칙적 종속성 (Regular Data Dependency)등으로 인한 실시간 고속 처리를 위한 VLSI 구현에 적합하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.3
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• pp.197-212
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• 1990

This paper present a new design concept of a single chip 16-bit data path using the concept of modular design, the whole system is divided into several blocks which can be operated as an independent system itself. Making the internal blocks can act as a subsystem, it is possible to shorten design turn-around time, to be redesigned effectively, and to optimize the system performance. The designed system is data path. The data path is to manipulate 16-bit integer data. It is composed of aritmetic logic unit, register file, barrel shifter and bus circuit. The widths and lengths of gate in the circuit were determined using SPICE2. The results of circuit simulation were in good agreement with expected circuit characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.835-838
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• 2013

클라우드 컴퓨팅을 사용하면 컴퓨팅 자원을 구축하는 비용을 절감할 수 있다는 장점이 있다. 문제는 클라이언트가 데이터 센터와 서비스제공자를 완전히 신뢰할 수 없다는 것이다. 예를 들어, 클라우드에 저장된 파일이 손실되었을 때 서비스 제공자는 서비스의 신뢰도가 떨어지는 것을 막기 위해 이를 숨길 수 있다. 이때, 데이터가 저장 후에 손실되었다는 것을 증명하지 못하면, 그 피해는 클라이언트에게 돌아오게 된다. 따라서, 클라이언트의 데이터를 보호하기 위하여 무결성을 검증할 수 있는 적절한 기법을 적용하여야 한다. 기존 연구로는 homomorphic tags 기반의 기법들이 많이 제안되었으나 이 기법은 많은 지수연산을 필요로 하므로 상용화할 수 있을 만큼의 효율성을 가지지 못한다. 특히, 클라이언트가 증거 생성을 위해 많은 연산을 부담해야 한다. 본 논문에서는 효율성에 중점을 둔, 특히 클라이언트의 효율성에 중점을 둔 무결성 검증 기법을 제안한다. 제안하는 기법은 Modular arithmetic을 기반으로 설계되었으며, 무결성 검증뿐만 아니라 데이터가 자주 업데이트 되는 환경을 지원한다. Simulation result는 제안하는 기법이 기존 기법에 매우 효율적임을 보여준다.