• Journal of Power Electronics
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• 제12권3호
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• pp.377-386
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• 2012

An interleaved bridgeless buck-boost AC/DC converter is presented in this paper to achieve the characteristics of low conduction loss, a high power factor and low harmonic and ripple currents. There are only two power semiconductors in the line current path instead of the three power semiconductors in a conventional boost AC/DC converter. A buck-boost converter operated in the boundary conduction mode (BCM) is adopted to control the active switches to achieve the following characteristics: no diode reverse recovery problem, zero current switching (ZCS) turn-off of the rectifier diodes, ZCS turn-on of the power switches, and a low DC bus voltage to reduce the voltage stress of the MOSFETs in the second DC/DC converter. Interleaved pulse-width modulation (PWM) is used to control the switches such that the input and output ripple currents are reduced such that the output capacitance can be reduced. The voltage doubler topology is adopted to double the output voltage in order to extend the useable energy of the capacitor when the line voltage is off. The circuit configuration, principle operation, system analysis, and a design example are discussed and presented in detail. Finally, experiments on a 500W prototype are provided to demonstrate the performance of the proposed converter.

• Journal of Power Electronics
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• 제13권4호
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• pp.619-625
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• 2013

Switched mode power supplies (SMPS) are power electronic circuits extensively used in a wide range of applications. High frequency switching operation of SMPS causes electromagnetic emissions and has the potential to interfere with system operation, which in turn has an impact on system performance. This makes electromagnetic compatibility (EMC) an important concern. In this paper, a new and simple spread spectrum technique is proposed by modulating chaotic pulse position modulation (CPPM) and pulse width modulation (PWM). The resulting CPWM is implemented to reduce the conducted EMI in SMPS. The proposed method is found to be effective in reducing conduction EMI. The effectiveness and simplicity of the proposed method on spreading those dominating frequencies is compared to the EMI mitigation technique using an external chaotic generator. Finally, the levels of conductive EMI with standard PWM, CPWM with an external chaos generator and the proposed method are experimentally verified to comply with the CISPR 22A regulations. The results confirm the effectiveness of the proposed method.

• Journal of Power Electronics
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• 제18권3호
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• pp.802-816
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• 2018

A digital direct phase-shift control (DDPSC) method based on the phase-shifted full-bridge LLC (PSFB-LLC) converter is presented. This work combines DDPSC with the conventional linear control to obtain a hybrid control strategy that has the advantages of linear control and DDPSC control. The strategy is easy to realize and has good dynamic responses. The PSFB-LLC circuit structure is simple and works in the fixed frequency mode, which is beneficial to magnetic component design; it can realize the ZVS of the switch and the ZCS of the rectifier diode in a wide load range. In this work, the PSFB-LLC converter resonator is analyzed in detail, and the concrete realization scheme of the hybrid control strategy is provided by analyzing the state-plane trajectory and the time-domain model. Finally, a 3 kW prototype is developed, and the feasibility and effectiveness of the DDPSC controller and the hybrid strategy are verified by experimental results.

• 대한기계학회논문집
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• 제13권2호
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• pp.213-220
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• 1989

본 연구에서는 고정도의 위치제어계를 실현하기 위하여 가변구조제어이론을 전기-유압서보계에 적용하였다.실험은 유압구동부의 공급압력을 변화시켜 유압계의 매개변수를 변화시켜줄 때와 관성하중을 가감하여 부하를 변화시켜 가며 행하였다. 가변구조계에서는 계의 매개변수변동과 부하변동에도 영향을 받지 않음을 종래의 고정구조계와 구조계와 비교, 검토하였다.

• International Journal of Aeronautical and Space Sciences
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• 제9권1호
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• pp.162-168
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• 2008

A design objective for variable stability flight control system is to develop a controller of in-flight simulation capability that forces the aircraft being flown to follow the dynamics of other aircraft. This paper presents a model-following variable stability control system (VSS) for in-flight simulation which consists of feedforward and feedback control laws, the aircraft dynamic model to be simulated, and switching and fader logics to reduce the transient effect between two aircraft dynamics. The separate design techniques for feedforward and feedback control law proposals are based on model matching and augmented linear quadratic (LQ) techniques. The system allows pilots to select and engage VSS mode, and when deselected, the aircraft reverts to the baseline flight control system. Both the baseline flight control laws and VSS control laws are computed continuously during flight. Initialization of the state values are necessary to prevent instability, since VSS control laws have integrators and filters in longitudinal, and lateral/directional axes. This paper demonstrates and validates the effectiveness and quality of VSS with F-16 models embedded in T-50 in-flight simulation aircraft.

• 한국통신학회논문지
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• 제23권6호
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• pp.1562-1574
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• 1998

본 논문에서는 ATM(Asynchronous Transfer Mode) 교환기 시스템에 T1, E1 및 부분적으로 E1급 속도의 중 저속 HDSL(High-rate digital subscriber line) 정합 기능을 개발하고, 근단누화(NEXT), 임펄스. 선로 잡음(power line noise) 및 접지 임피던스(longitudinal) 잡음 같은 주요 전송 손실이 존재하는 0.4 mm 및 0.5 mm의 기존 전화가입자 선로(UTP, Unshielded twisted pair)를 사용하는 CSA(Carrier serving areas) 선로 모델을 이용하여 $10^{-7}$의 BER(Bit error rates)의 전송 성능을 만족하기 위한 가입자 서비스 전송 거리 성능을 평가하였다. HDSL은 DSI, ISDN 기본 속도 접속 및 DLC 피더에 사용될 것이며 광 케이블과 인터페이스될 것이다. 또한, HDSL 시잔 전망을 제시한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.160-163
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• 2004

A passive lossless turn-on/turn-off snubber network is proposed for the boost PWM converter. Previous AC/DC PFC Boost Converter perceives feed forward signal of output for average current-mode control. Previous Boost Convertor, the Quantity of input current will be decreased by the decrease of output current in light load, and also Power factor comes to be decreased. Also the efficiency of converter will be decreased by the decrease of power factor. The proposed converter presents the good PFC, low line current harmonic distortions and tight output voltage regulations using energy recovery circuit. All of the semiconductor devices in the converter are turned on under exact or near zero voltage switching(ZVS). No additional voltage and current stresses on the main switch and main diode occur. To show the superiority of this converter is verified through the experiment with a 640W, 100kHz prototype converter.

• 한국화재소방학회논문지
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• 제17권4호
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• pp.98-104
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• 2003

대구 지하철역 제연의 문제점과 그 대책을 조사하기위해 지하철역 승강장 계단 주위 10 m${\times}$3 m${\times}$5.4 m 의 공간에서의 제연을 FDS로 모사하였다. 200 ㎾의 폴리우레탄 화재와 각 급기구와 배기구의 공기유량 0.9 ㎥/s에 대한 급기방식의 제연성능을 온도와 연기입자의 분포로 조사한 결과, 급기방식은 제연효과가 거의 없어 연기를 신속하게 배출하지 못함을 알 수 있었다. 또 세가지 기계제연방식 중에서 배기방식의 제연성능이 가장 우수하므로, 급기방식을 단순히 배기방식으로 전환함으로써 제연성능을 대폭 개선할 수 있음을 확인하였다.

• Journal of international Conference on Electrical Machines and Systems
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• 제1권3호
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• pp.372-378
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• 2012

This paper deals with a 3-phase voltage disturbance generator for a performance test of custom power devices such as dynamic voltage restorers (DVR), dynamic uninterruptable power supplies (UPS), etc. The operating principle of the proposed circuit is described in each mode of voltage sag, swell, outage, and unbalance. The main components of the proposed disturbance generator are silicone controlled rectifier (SCR) thyristors, variable autotransformers, and transformers. Therefore, the disturbance generator can be implemented with a considerably low cost compared to the conventional pulse width modified (PWM) inverter and converter type generators. Furthermore, it has good features of high reliability with simple structure, high efficiency caused by no PWM switching of the SCR thyristors, and easy control with a wide variation range. To verify the validity of the proposed scheme, simulations and experiments are carried out.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.607-608
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• 2006

A CMOS phase-locked loop (PLL) which synthesizes frequencies between $6.336{\sim}8.976GHz$ in steps of 528MHz and settles in approximately 150ns using the 528MHz reference clock is presented. Frequency hopping between the bands in the each mode is critical point to design the PLL in multi-band orthogonal frequency division multiplexing (OFDM) because frequency switching between each band is less than 9.5ns. To achieve the fast loop settling, integer-N PLL that operates with the high reference frequency to meet the settling requirement is implemented. Two PLLs that operate at 9GHz and 528MHz is integrated and shows the band hopping lower than 1ns.