• Journal of Power Electronics
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• v.9 no.1
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• pp.43-50
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• 2009

This paper deals with a novel solid state controller (NSSC) for an isolated asynchronous generator (IAG) feeding 3-phase 4-wire loads driven by constant power prime movers, such as uncontrolled pico hydro turbines. AC capacitor banks are used to meet the reactive power requirement of the asynchronous generator. The proposed NSSC is realized using a set of IGBTs (Insulated gate bipolar junction transistors) based current controlled 2-leg voltage source converters (CC- VSC) and a DC chopper at its DC bus, which keeps the generated voltage and frequency constant in spite of changes in consumer loads. The neutral point of the load is created using aT-configuration of the transformers. The IAG system is modeled in MATLAB along with Simulink and PSB (power system block set) toolboxes. The simulated results are presented to demonstrate the capability of the isolated generating system consisting of NSSC and IAG driven by uncontrolled pico hydro turbine and feeding 3-phase 4-wire loads.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.220-228
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• 1995

An optimized 4-stage 12-bit pipelined CMOS analog-to-digital converter (ADC) architecture is proposed to obtain high linearity and high yield. The ADC based on a multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted-capacitor (BWC) array in the front-end stage and a unit-capacitor (UC) array in the back-end stages to improve integral nonlinearity (INL) and differential nonlinearity (DNL) simultaneously whil maintaining high yield. A digital-domain nonlinear error calibration technique is applied in the first stage of the ADC to improve its accuracy to 12-bit level. The largest DNL error in the mid-point code of the ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is simulated to prove the effectiveness of the proposed ADC architecture.