• 제목/요약/키워드: Microprocessors

검색결과 203건 처리시간 0.033초

256-channel 1 ksamples/sec 심자도 신호획득 시스템 (256-channel 1ks/s MCG Signal Acquisition System)

  • 이동하;유재택;허영
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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    • pp.538-540
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    • 2004
  • Electrical currents generated by human heart activities create magnetic fields represented by MCG(MagnetoCardioGram). Since an MCG signal acquisition system requires precise and stable operation, the system adopts hundreds of SQUID(Superconducting QUantum Interface Device) sensors for signal acquisition. Such a system requires fast real-time data acquisition in a required sampling interval, i.e., 1 mili-second for each sensor. This paper presents designed hardware to acquire data from 256-channel analog signal with 1 ksamples/sec speed, using 12-bit 8-channel ADC devices, SPI interfaces, parallel interfaces, 8-bit microprocessors, and a DSP processor. We implemented SPI interface between ADCs and a microprocessor, parallel interfaces between microprocessors. Our result concludes that the data collection can be done in $168{\mu}sec$ time-interval for 256 SQUID sensors, which can be interpreted to 6 ksamples/sec speed.

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Study of Modular Multiplication Methods for Embedded Processors

  • Seo, Hwajeong;Kim, Howon
    • Journal of information and communication convergence engineering
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    • 제12권3호
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    • pp.145-153
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    • 2014
  • The improvements of embedded processors make future technologies including wireless sensor network and internet of things feasible. These applications firstly gather information from target field through wireless network. However, this networking process is highly vulnerable to malicious attacks including eavesdropping and forgery. In order to ensure secure and robust networking, information should be kept in secret with cryptography. Well known approach is public key cryptography and this algorithm consists of finite field arithmetic. There are many works considering high speed finite field arithmetic. One of the famous approach is Montgomery multiplication. In this study, we investigated Montgomery multiplication for public key cryptography on embedded microprocessors. This paper includes helpful information on Montgomery multiplication implementation methods and techniques for various target devices including 8-bit and 16-bit microprocessors. Further, we expect that the results reported in this paper will become part of a reference book for advanced Montgomery multiplication methods for future researchers.

최신 마이크로프로세서상에서 LU-SGS 코드의 국소화 작성 (Localized Composition of LU-SGS Code on Latest Microprocessors)

  • 최정열
    • 한국전산유체공학회:학술대회논문집
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    • 한국전산유체공학회 2001년도 춘계 학술대회논문집
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    • pp.45-50
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    • 2001
  • An approach of composing a performance optimized computational code is suggested for latest microprocessors. The approach named as localization is a concept of minimizing the access to system's main memory and maximizing the utilization of second level cache that is common to all the latest computer system. The localized compositions of LU-SGS scheme for fluid dynamics were made in three different levels and tested on three different microprocessor architectures most widely used in these days. The test results of localization concept showed a remarkable performance, that is the showing gain up to 4.5 times faster solution than the baseline algorithm $450\%$ for producing an exactly the same solution.

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심자도 신호 획득을 위한 실시간 64-Ch 12-bit 1ks/s 하드웨어 개발 (Development of 64-Channel 12-bit 1ks/s Hardware for MCG Signal Acquisition)

  • 이동하;유재택
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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    • pp.902-905
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    • 2004
  • A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUID) sensors for precision MCG signal acquisitions. Such system is composed of hundreds of sensors, requiring fast signal sampling and precise analog-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit 1ks/s, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 ms speed. The test result shows that the signal acquisition is done in 168 usuc which is much shorter than the required 1 ms period. This hardware will be extended to 256 channel data acquisition to be used for the diagnosis system.

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삼타어뢰의 퍼지제어를 위한 실시간 시뮬레이션 (Real-time simulation for fuzzy control of three fin torpedo)

  • 남세규;원태현;구본순;이만형;유완석
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
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    • pp.869-873
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    • 1992
  • A fuzzy controller is designed for compensating the cross-coupling effect of induced roll due to the dynamic characteristics of three fin torpedo. Since the utilization of fuzzy-coprocessor has many interfacing problems with typical microprocessors of the guidance and control unit, the simplified fuzzy inference method based on nonfuzzy-processor is proposed to implement fuzzy controllers of three fin torpedo. This method provides a flexible rule-base design to guarantee the robust control. The good potential of the proposed design is shown through real-time simulations using both a mathematical model on AD-100 computer and an implemented controller on Intel 80C186/80C 187 microprocessors employing 12bit A/D converter.

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마이크로프로세서 디지털 입력포트에 대한 히스테리시스 특성 부여방법에 관한 연구 (A Study on the Method of Giving Hysteresis Characteristics to the Digital input port of Microprocessors)

  • 이현창
    • 전자공학회논문지SC
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    • 제48권2호
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    • pp.56-63
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    • 2011
  • 본 논문에서는 마이크로프로세서의 디지털 입력포트에 히스테리시스 특성을 부여하는 방법 및 설계 순서를 제시하고 이를 실험해 그 효과를 확인하였다. 프로세서의 잉여포트가 있을 때 제시한 방법을 이용하면 저항 2개의 추가만으로 히스테리시스 특성을 얻을 수 있으며, 더구나 기존의 TTL과 CMOS의 슈미트 트리거 게이트에 비해 큰 히스테리시스 폭을 얻을 수 있다.

Adopting the Banked Register File Scheme for Better Performance and Less Leakage

  • Jang, Hyung-Beom;Chung, Eui-Young;Chung, Sung-Woo
    • ETRI Journal
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    • 제30권4호
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    • pp.624-626
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    • 2008
  • Excessively high temperature deteriorates the reliability and increases the leakage power consumption of microprocessors. The register file, known as one of the hottest functional units in microprocessors, incurs frequent dynamic thermal management operations for thermal control. In this letter, we adopt the banked register file scheme, which was originally proposed to reduce dynamic power consumption. By simply modifying the register file structure, the temperature in the register file was reduced dramatically, resulting in 13.37% performance improvement and 10.49% total processor leakage reduction.

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한글 문자의 생성을 위한 하드웨어 가속기 개발 (Development of a Hardware Accelerator for Generation of Korean Character)

  • 이태형;황규철;이윤태;배종홍;경종민
    • 전자공학회논문지B
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    • 제28B권9호
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    • pp.712-718
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    • 1991
  • In this paper, we propose a graphic system for high speed generation of bitmap font data from the outline font data such as PostScript, etc. In desk-top publishing system. A VLSI chip called KAFOG was designed for the high-speed calculation of a cubic Bezier curve, which was implemented in 1.5\ulcorner CMOS gate array using 17,000 gates. A cubic Bezier curve is approximated by a set of line segments in KAFOG at the throughput of 250K curves per second with the clock frequency of 40 MHz. A prototype graphic system was developed using two MC6800 microprocessors and the KAFOG chip. Two microprocessors cooperate in a master and slave mode, and handshaking is used for communication between two processors. KAFOG chip, being controlled by the slave processor, operates as a coprocessor for the calculation of the outline font. The throughput of the prototype graphic system is 40 64$\times$64 outline fonts per sencond.

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심자도 신호 획득을 위한 고속 병렬 데이터 전송 구현 (Implementation of high-speed parallel data transfer for MCG signal acquisition)

  • 이동하;유재택
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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    • pp.444-447
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    • 2004
  • A heart diagnosis system adopts hundreds of Superconducting Quantum Interface Device(SQUID) sensors for precision MCG(Magnetocardiogram) or MEG(Magnetoencephalogram) signal acquisitions. This system requires correct and real-time data acquisition from the sensors in a required sampling interval, i.e., 1 mili-second. This paper presents our hardware design and test results, to acquire data from 256 channel analog signal with 1-ksample/sec speed, using 12-bit 8-channel ADC devices, SPI interfaces, parallel interfaces, and 8-bit microprocessors. We chose to implement parallel data transfer between microprocessors as an effective way of achieving such data collection. Our result concludes that the data collection can be done in 250 ${\mu}sec$ time-interval.

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