• 제목/요약/키워드: Microprocessors

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JOINT POSITION COMTROL SYSTEM FOR FARA ROBOTS OF SAMSUNG ELECTROICS

  • Kim, Hyo-Kyu;Kim, Dong-Il;Kim, Sungkuwn
    • 제어로봇시스템학회:학술대회논문집
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    • 1990.10b
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    • pp.913-916
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    • 1990
  • In this paper, attempts have been made to control AC synchronous servo motor used as actuators of joints of the FARA robot with high dynamic performance and precise positioning. The AC synchronous servo motors used in FARA robots have resolves as position sensors. Resolver to digital converters are used in order to obtain the information of rotor speed and position from resolver outputs. The proposed joint position control system consists of four speed controller and one position controller. Analog methods are used in the position controller, while digital methods are used in the position controller. For precise position control, PID control algorithm and interpolation functions are executed in two 16 bit microprocessors with sampling rate 2ms. Experimental results show that the proposed joint position control system can be effectively applied to industrial robots in order to obtain high dynamic performance and precise positioning. The proposed joint position control system is being used in the control of FARA robots of Samsung Electronics.

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17$\times$17-b Multiplier for 32-bit RISC/DSP Processors (32 비트 RISC/DSP 프로세서를 위한 17 비트 $\times$ 17 비트 곱셈기의 설계)

  • 박종환;문상국;홍종욱;문병인;이용석
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.914-917
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    • 1999
  • The paper describes a 17 $\times$ 17-b multiplier using the Radix-4 Booth’s algorithm. which is suitable for 32-bit RISC/DSP microprocessors. To minimize design area and achieve improved speed, a 2-stage pipeline structure is adopted to achieve high clock frequency. Each part of circuit is modeled and optimized at the transistor level, verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, we lay it out in a 0.35 ${\mu}{\textrm}{m}$ 1-poly 4-metal CMOS technology and perform LVS test to compare the layout with the schematic. The simulation results show that maximum frequency is 330MHz under worst operating conditions at 55$^{\circ}C$ , 3V, The post simulation after layout results shows 187MHz under worst case conditions. It contains 9, 115 transistors and the area of layout is 0.72mm by 0.97mm.

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Design and manufacture of atomatic microwave leakage inspection system (전자 오븐의 누설 고주파 자동 검사 시스템 설계와 제작)

  • 이만형;송지복;이석희;정영철;안희태
    • 제어로봇시스템학회:학술대회논문집
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    • 1987.10b
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    • pp.492-496
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    • 1987
  • The testing philosophy and control schemes are investigated and applied to construct the Automatic Microwave Leakage Inspection System (AMLIS) . AMLIS is consists of three major parts such as Material Handling Mechanism, Fine Positioning Mechanism and Scanning Mechanism. The material Handling unit is designed to perform loading and unloading microwave oven onto the testing point by pneumatic cylinder and vacuum pump. The Fine positioning part includes X-Y-.THETA. table and distance sensing equipment. The scanning part is composed of five SCARA robots, which traverse X-Y-Z catesian coordinates respectively. The leakage testing probes are placed at the end of this each robot then the path and speed are both controlled via microprocessors. A performance test of this system combined with electric parts and software is done and the basic major function of system are accomplished.

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The analysis of MPPT algorithms (최대전력추종제어기법 비교 분석)

  • Lee, Kyung-Soo;Jung, Young-Seck;So, Jung-Hoon;Yu, Gwon-Jong;Choi, Jae-Ho
    • Proceedings of the KIEE Conference
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    • 2004.04a
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    • pp.212-214
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    • 2004
  • As the maximum power operating point(MPOP) of photovoltaic(PV) power generation systems changes with changing atmospheric conditions such as solar radiation and temperature, an important consideration in the design of efficient PV system is to track the MPOP correctly. Many maximum power point tracking(MPPT) techniques have been considered in the past, however, techniques using microprocessors with appropriate MPPT algorithms are favored because of their flexibility and compatibility with different PV arrays. Although the efficiency of these MPPT algorithms is usually high, it drops noticeably in case of rapidly changing atmospheric conditions. This paper analysed and researched the characteristics of three MPPT algorithms; P&O, Inc&Cond, ImP&O and simulated them with irradiance changing.

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A New MPPT Algorithm based on P&O Algorithm (P&O 알고리즘을 개선한 새로운 MPPT 알고리즘)

  • Jung Y.S.;Yu G.J.;So J.H.;Choi J.Y.;Choi J.H.
    • Proceedings of the KIPE Conference
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    • 2003.07b
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    • pp.925-928
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    • 2003
  • As the maximum power operating point(MPOP) of photovoltaic(PV) power generation systems changes with changing atmospheric conditions such as solar radiation and temperature, an important consideration in the design of efficient PV system is to track the MPOP correctly. Many maximum power point tracking(MPPT) techniques have been considered in the past, however, techniques using microprocessors with appropriate MPPT algorithms are favored because of their flexibility and compatibility with different PV arrays. Although the efficiency of these MPPT algorithms is usually high, it drops noticeably in case of rapidly changing atmospheric conditions. This paper proposed a new MPPT algorithm based on perturb & observe(P&O) algorithm with experiment. The results shows that the new P&O algorithm has successfully tracked the MPOP, even in case of rapidly changing atmospheric conditions, and has higher efficiency than ordinary algorithms.

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Comparative Study of Maximum Power Point Tracking Algorithms Using PV Array Simulator (태양전지 모의 전원을 이용한 MPPT 알고리즘의 비교 고찰)

  • Jung Youngseok;So Junghun;Yu Gwonjong;Choi Jaeho
    • Proceedings of the KIPE Conference
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    • 2003.11a
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    • pp.234-237
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    • 2003
  • As the maximum power operating point (MPOP) of photovoltaic (PV) power systems changes with changing atmospheric conditions, the efficiency of maximum power point tracking (MPPT) is important in PV power systems. Many MPPT techniques have been considered in the past, but techniques using microprocessors with appropriate MPPT algorithms are favored because of their flexibility and compatibility with different PV arrays. Although the efficiency of these MPPT algorithms is usually high, it drops noticeably in case of rapidly changing atmospheric conditions. In this paper, we proposed a new MPPT control method called improved perturb and observe method (ImP&O), anda simple voltage and current characteristic equation of a PV array for PV array simulator. Experimental results verify the accuracy and excellent performance of the proposed MPPT method. ImP&O algorithm is very simple, and has successful tracked the MPOP, even in case of rapidly changing atmospheric conditions.

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Design of a Remote Lighting Control System Using Time Division Multiplex Transmission (시분할 다중 전송방식을 이용한 원격 조명제어 설계)

  • 정성재;김일환
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.33-33
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    • 2000
  • In this paper a new distributive control system for BA(Building Automation ) lighting control used on general microprocessors is presented. For optimal lighting control and saving energy, The system have to control the group and pattern lighting control as well as individual light control at one time. Tn this paper, This functions are accomplished with low-cost and simple microprocessor. A plurality of modulated light control terminals are connected to the central control unit through a pair of power line. This power line provide both power and signal to the each terminal and the data is transmitted through cyclic time division multiplex transmission. With this structure a low-cost distributive control system for lighting applications has been achieved, allowing energy and maintenance saving and reliability increase of the light control system.

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Development of RSFQ Logic Circuits and Delay Time Considerations in Circuit Design (RSFQ 논리회로의 개발과 회로설계에 대한 지연시간 고려)

  • Kang, J.H.;Kim, J.Y.
    • Progress in Superconductivity
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    • v.9 no.2
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    • pp.157-161
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    • 2008
  • Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

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A compatibility verification environment for HDL-modeled microprocessors

  • 이문기;김영완;서광수;손승일
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.2
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    • pp.409-416
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    • 1996
  • This paper describes the simulation environment that verifies whether a new microporcessor described with HDL is compatible with an existing microprocessor. The compatibility verification is done by showing that the new microprocessor executes the OS(Operating System) program used in the existing microprocessor without any modification of its binary code. The proposed verification environment consists of a virtual system and a graphic user interface (GUI) module. Each module is independently designed based on serve-client model and three exists a communication part for information interchange between the two modules. This paper describes the method of constructing the verification environment and presents the compatibility verification environment of the x86 microprocessor as the simulation result.

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Design of SIMD-DSP/PPU for a High-Performance Embedded Microprocessor (고성능 내장형 마이크로프로세서를 위한 SIMD-DSP/FPU의 설계)

  • 정우경;홍인표;이용주;이용석
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.4C
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    • pp.388-397
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    • 2002
  • We designed a SIMD-DSP/FPU that can efficiently improve multimedia processing performance when integrated into high-performance embedded microprocessors. We proposed partitioned architectures and new schemes for several functional units to reduce chip area. Sharing functional units reduces the area of FPU significantly. The proposed architecture is modeled in HDL and synthesized with a 0.35$\mu\textrm{m}$ standard cell library. The chip area is estimated to be about 100,000 equivalent gates. The designed unit can run at higher than 50MHz clock frequency of CPU core under the worst-case operating conditions.