• 대한전자공학회논문지
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• 제13권2호
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• pp.28-33
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• 1976

최근, Microprocessor가 염가로 입수가능함에 따라 광범위한 분야에 걸쳐서 사용되고 있다. microprocessor를 유효하게 사용하면 컴퓨터 시스템의 설계가 용이해진다. 이 논문에서는 MMI-6701을 사용하여 NOVA의 Emulator를 설계 하였으며 연구의 성과로서는 NOVA를 Microprocessor로 대치하므로서 IC의 수가 약 3분의 1로 대치할 수 있었고, 또 Emulator의 효율화를 위하여 PROM의 Micro명령은 32bit로서 구성하여 4종류의 명령형식으로 설계 되였다. In recent years, Microprocessor have the use of extended wide fiexd because of obtainable to low price. Design of computer system be easy to do by this microprocessor apply validly. This Papers: NOVA Emulator designed by use of MMI-6701. As a result of this studies, quantity of IC changed with about a third part by NOVA exchanged with Microprocessor. Micro Instruction of PROM consist of 32bit that designed Instruction Format of four kinds.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 1998년도 가을 학술발표논문집 Vol.25 No.2 (3)
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• pp.18-20
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• 1998

본 논문에서는 RISC Microprocessor Core 설계에 대한 기반 기술을 확립하여, GPS(Global Positioning System) 같은 Embedded 시스템 등에서 주로 사용되어 지고 있는 ARM사의 ARM7 CPU와 이진 호환이 가능한 Microprocessor를 설계하고자 하였다. 이를 위하여 RISC Microprocessor의 기본적인 구조를 바탕으로 하여 ARM7 CPU와의 호환을 위하여 ARM7 CPU의 명령어들이 주어진 Clock안에 수행될 수 있도록 설계를 하였고, 여러 모듈을 원활히 공유할 수 있도록 내부에 공유 버스를 설계하였다. 설계를 위해서 Verilog-HDL(Hardware Description Language)을 사용하였으며, Microprocessor를 기술하는데 있어서 Behavioral 구조와 RTL(Register Transfer Level) 구조를 혼합하여 사용하였다. 설계된 Microprocessor의 동작은 면적과 타이밍의 최적화를 거친 후 Cwaves 툴을 사용하여 실질적인 ARM7의 명령어들을 수행하면서 검증하였다.

• 품질경영학회지
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• 제28권1호
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• pp.27-40
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• 2000

Technological forecasting for microprocessor market can provide timely insight into the prospects for significant technological changes in computer hardware as well as software. In this paper, we use bibliometrics to forecast R&D trend on microprocessor technology. Cumulative numbers of US Patents on several generations of microprocessor technology (pipeline, superpipeline, supersclar and VLIW) approved since 1980 are applied to fit diffusion models. Our study results provide both the maximum market potential and the maturity time for each generation of microprocessor technology. Such information is expected to make contribution on making better decisions with regard to strategic corporate planning, R&D management, product development and investment in new technology of microprocessor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.408-411
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• 1999

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 B
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• pp.637-639
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• 1998

Educational software tends to be monotonous without the interaction between instructors and students. An unidirectional teaching system can't overcome these barriers because the learning process is monotonous without the bidirectional communication. The advanced network system can solve these problems. In this study, a bidirectional microprocessor simulator is developed and a new teaching model is proposed using the simulator. It was named JMPS (Java Microprocessor Simulator), which is a software to teach the microprocessor principles and applications. It has two advantages. First, it can teach the principles and applications of microprocessor effectively. Second, it runs on Internet and provides easy communication between a teacher and students.

• 대한전자공학회논문지SD
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• 제41권4호
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• pp.83-90
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• 2004

본 논문은 메모리 크기의 제약을 많이 받는 내장형 마이크로프로세서의 문제를 해결하기 위해 32-bit 명령어와 24-bit, 16-bit 명령어를 혼합 사용하여 3가지 명령어 모드를 갖는 새로운 명령어 셋(X32V ISA)을 제안하였으며, 이를 기반으로 32-bit 5 stage pipeline RISC 마이크로프로세서를 설계하였다. 이를 검증하기 위해서 X32V ISA 전용 시뮬레이터를 이용하여 멀티미디어 프로그램의 프로그램 코드 사이즈를 산출하였다. 그 결과로 Light mode와 Ultra light mode는 Default mode에 비해 각각 최소 8%, 27%의 프로그램 코드 사이즈 감소를 확인하였으며, Xilinx FPGA를 이용하여 33MHz 동작 환경에서 X32V ISA의 모든 명령어 수행을 검증하였다.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• 제2B권4호
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• pp.207-213
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• 2002

The paper introduces a switched reluctance motor drive system based on an 80C31 and an Intel 80C 196KB single-chip microprocessor control. Advance schemes are used in turn-on and turn-off angles with the power converter's main switches during traction and regenerative braking. The principles of traction speed control and braking torque control are given. The hardware and software patterns in the 80c31 and the Intel 80C196KB single-chip microprocessor control system are also presented.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.333-336
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• 2002

This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.

• ETRI Journal
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• 제26권6호
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• pp.513-519
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• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.885-888
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• 2005

In this study, we designed an ARM9 compatible RISC microprocessor using VHDL. The microprocessor was designed to support Harvard architecture with separate instruction cache and data cache. The state machine was optimized for multi-cycle instructions. In addition, a data forwarding mechanism was adopted to reduce the stall cycles due to data hazards. Assembly programs were up-loaded into a ROM block for system-level simulation. Proper operation of the designed microprocessor was confirmed by investigating the contents of the internal registers as well as the RAM block. Futhermore, the simulation results clearly indicated that the operation speed of the processor designed in this study is enhanced by reducing the execution cycles required for multiplication related instructions.