• Title/Summary/Keyword: Microelectronic packaging

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Nanocomposites for microelectronic packaging

  • Lee, Sang-Hyeon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.99.1-99.1
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    • 2016
  • The materials for an electronic packaging provide diverse important functions including electrical contact to transfer signals from devices, isolation to protect from the environment and a path for heat conduction away from the devices. The packaging materials composed of metals, ceramics, polymers or combinations are crucial to the device operating properly and reliably. The demand of effective charge and heat transfer continuous to be challenge for the high-speed and high-power devices. Nanomaterials including graphene, carbon nanotube and boron nitride, have been designed for the purpose of exploiting the high thermal, electrical and mechanical properties by combining in the matrix of metal or polymer. In addition, considering the inherent electrical and surface properties of graphene, it is expected that graphene would be a good candidate for the surface layer of a template in the electroforming process. In this talk, I will present recent our on-going works in nanomaterials for microelectronic packaging: 1) porous graphene/Cu for heat dissipations, 2) carbon-metal composites for interconnects and 3) nanomaterials-epoxy composites as a thermal interface materials for electronic packaging.

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Via Filling in Fine Pitched Blind Via Hole of Microelectronic Substrate (마이크로 전자기판의 미세 피치 블라인드 비아홀의 충진 거동)

  • Yi Min-Su;Lee Hyo-S.
    • Journal of the Microelectronics and Packaging Society
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    • v.13 no.1 s.38
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    • pp.43-49
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    • 2006
  • The properties, behavior and reliability of the residual void in blind via hole(BVH) were carried out for the shape of BVH using the void extraction process. The residual void was perfectly removed in the specimens applied by the void extraction process, which was improved by 40% rather than the conventional process. The residual void in BVH was to be eliminated under a condition of 1.5 atm for more 30 sec with regardless of the shape of BVH. It was also observed that the residual void in BVH was not formed after the reliability test with JEDEC standard.

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Study on the Prediction of Fatigue Life of BGA Typed Solder Joints (BGA 형태 솔더 접합부의 피로 수명 예측에 관한 연구)

  • Kim, Seong-Keol;Kim, Joo-Young
    • Transactions of the Korean Society of Machine Tool Engineers
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    • v.17 no.1
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    • pp.137-143
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    • 2008
  • Thermal fatigue life prediction for solder joints becomes the most critical issue in present microelectronic packaging industry. And lead-free solder is quickly becoming a reality in electronic manufacturing fields. This trend requires life prediction models for new solder alloy systems. This paper describes the life prediction models for SnAgCu and SnPb solder joints, based upon non-linear finite element analysis (FEA). In case of analyses of the SnAgCu solder joints, two kinds of shapes are used. As a result, it is found that the SnAgCu solder has longer fatigue life than the SnPb solder in temperature cycling analyses.

Thermophysical Properties of PWB for Microelectronic Packages with Solder Resist Coating Process (마이크로 전자패키지용 Printed Wiring Board의 솔더레지스트공정에 따른 열적특성)

  • 이효수
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.3
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    • pp.73-82
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    • 2003
  • Recently, PWB(Printed Wiring Board) has been recognized in the field of microelectronic package as core technology for designing or manufacturing. PWB is the structure stacked by several materials with different thermophysical properties, which shows the different CTEs(Coefficient or Thermal Expansions) during the fabrication process and causes a lot of defects such as warpage, shrinkage, dimension, etc. Thermal deformation of PWB is affected mainly by the volume change of solder-resist among fabrication parameters. Therefore, thermal deformation of PBGA and CSP consisting of 2 layers and 4 layers was studied with solder-resist process. When over 30% in volume fraction of solder-resist, thermal deformation of 2-layered PWB was min. 40% higher than that of 4-layered PWB because 4-layered PWB contained the layer with high toughness such as prepreg, which counterbalanced the thermal deformation of solder-resist. Otherwise, when below 30%, PWB showed similar thermal deformation without regard to layers and design.

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Effect of High Filler Loading on the Reliability of Epoxy Holding Compound for Microelectronic Packaging (반도체 패키지 봉지재용 에폭시 수지 조성물의 신뢰특성에 미치는 실리카 고충전 영향)

  • 정호용;문경식;최경세
    • Journal of the Microelectronics and Packaging Society
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    • v.6 no.3
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    • pp.51-63
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    • 1999
  • The effects of high filler loading technique on the reliability of epoxy molding compound (EMC) as a microelectronic encapsulant was investigated. The method of high filler loading was established by the improvement of maximum packing fraction using the simplified packing model proposed by Ouchiyama, et al. With the maximum packing fraction of filler, the viscosity of EMC wart lowered and the flowability was improved. As the amount of filler in EMC increased, several properties such as internal stress and moisture absorption were improved. However, the adhesive strength with the alloy 42 leadframe decreased when the filler content was beyond the critical value. It was found that the appropriate content of filler was important to improve the reilability of EMC, and the optimum filler combination should be selected to obtain high reliable EMC filled with high volume fraction of filler.

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Current Status of Semiconductor and Microelectronic Packaging Technology Development in Korea

  • Sun, Yong-Bin
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.05a
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    • pp.1-6
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    • 2002
  • It is very important to foresee the main stream of technology development in the future. Packaging related manufacturers in equipment and materials focused their strength on products sharing big portion of world markets. As a result, domestic supply sources for packaging materials and equipment has been increased, but the manufacturer's capital and manpower is so limited to develop high technology machinery and high functional materials. The current status of packaging infrastructures in Korea is reviewed statistically. The hot issues in packaging arena are now in wafer level packaging, 3D packaging, and ultra-thin packaging. In addition, the recent advancement in microelectronics packaging technology is also covered.

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