• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• Journal of Navigation and Port Research
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• v.33 no.9
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• pp.635-644
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• 2009

The optimum design of power yacht belongs to the nonlinear constrained optimization problems. The determination of scantlings for the bow structure is a very important issue with in the whole structural design process. The derived design results are obtained by the use of real-coded micro-genetic algorithm including evaluation from Lloyd's Register small craft guideline, so that the nominal limiting stress requirement can be satisfied. In this study, the minimum volume design of bow structure on the power yacht was carried out based on the finite element analysis. The target model for optimum design and local structural analysis is the bow structure of a power yacht. The volume of bow structure and the main dimensions of structural members are chosen as an objective function and design variable, respectively. During optimization procedure, finite element analysis was performed to determine the constraint parameters at each iteration step of the optimization loop. optimization results were compared with a pre-existing design and it was possible to reduce approximately 19 percents of the total steel volume of bow structure from the previous design for the power yacht.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.470-476
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• 2000

This paper describes an IP design of a low-power microcontroller using an architecture level design methodology instead of a transistor level. To reduce switching capacitance, the register-toregister data transfer is adopted to frequently used register transfer micro-operations. Also, distributed buffers are proposed to reduce a input data rising edge time. To reduce power consumption without any loss of performance, pipeline processing should be used. In this paper, a 4-stage pipelined datapath being able to process CISC instructions is designed. Designed microcontroller lessens power consumption by 20%. To measure a power consumption, the SYNOPSYS EPIC powermill is used.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.512-522
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• 2003

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Typically, the size of the chip required to implement the circuit depends on both the maximum number of the LUT blocks required to implement the function of each subcircuit and the maximum number of micro-registers to store results over context switches in the same time. Therefore, many partitioning or synthesis methods try to minimize these two factors. In this paper, we present a new estimation technique to find the lower bound on the number of micro-registers which can be obtained by any synthesis methods, respectively, without performing any actual synthesis and/or design space exploration. The lower bound estimation is very important in sense that it greatly helps to evaluate the results of the previous work and even the future work. If the estimated lower bound exactly matches the actual number in the actual design result, we can say that the result is guaranteed to be optimal. In contrast, if they do not match, the following two cases are expected: we might estimate a better (more exact) lower bound or we find a new synthesis result better than those of the previous work. Our experimental results show that there are some differences between the numbers of micro-registers and our estimated lower bounds. One reason for these differences seems that our estimation tries to estimate the result with the minimum micro-registers among all the possible candidates, regardless of usage of other resources such as LUTs, while the previous work takes into account both LUTs and micro-registers. In addition, it implies that our method may have some limitation on exact estimation due to the complexity of the problem itself in sense that it is much more complicated than LUT estimation and thus needs more improvement, and/or there may exist some other synthesis results better than those of the previous work.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.597-598
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• 2008

In this paper, a sample design of I/O port of micro-processor using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. This paper also shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 37.5%

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.194-198
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• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• Proceedings of the KOSOMBE Conference
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• v.1997 no.11
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• pp.424-427
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• 1997

Electrical impedance plethysmography is still be one of the simplest and most convenient methods or non-invasive measurement of blood low, but it has the weak point can not do real-time measurement because of using chart-record or processing after receiving data from analog plethysmography through A/D converter. In this study. we developed hardware system composed of analog part which include auto-balancing circuit and calibration register and digital part which include 80C196KC, keypad, and LCD. we studied the algorithms or extracting parameter to calculate blood low and implemented it using general purpose micro controller.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.61-63
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• 1987

In this paper, we develope a system which can perform signal processing for bar-code laser scanner. This system is composed of optical detector and preprocessor. The former detects the diffused light and converts it into TTL lebel output. The latter discriminator valid data from various raw data and transmits data to micro-processor. The preprocessor consists of edge transition detector, latch signal generator, module counter, register array, adder array, and buffer memory control circuit etc..

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.466-476
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• 1986

This paper proposes a system that translates the machine independent intermediate micro-programming language(IML) into microcode, using the register allocation algorithm, the microinstruction format and the field information for the target machine emulation on a microprogrammable host machine. The IML, which is for PDP-8 emulation on a microprogrammable hypothsetical 16 bit host machine, is microcoded by the proposed system, and the validity of the algorithm in the proposed system is verified by executing a test program of the target machine on the emulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors