• Title/Summary/Keyword: Micro:bit

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Analog-Digital Signal Processing System Based on TMS320F28377D (TMS320F28377D 기반 아날로그-디지털 신호 처리 시스템)

  • Kim, Hyoung-Woo;Nam, Ki Gon;Choi, Joon-Young
    • IEMEK Journal of Embedded Systems and Applications
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    • v.14 no.1
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    • pp.33-41
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    • 2019
  • We propose an embedded solution to design a high-speed and high-accuracy 16bit analog-digital signal processing interface for the control systems using various external analog signals. Choosing TMS320F28377D micro controller unit (MCU) featuring high-performance processing in the 32-bit floating point operation, low power consumption, and various I/O device supports, we design and build the proposed system that supports both 16-bit analog-digital converter (ADC) interface and high precision digital-analog converter (DAC) interface. The ADC receives voltage-level differential signals from fully differential amplifiers, and the DAC communicates with MCU through 50 MHz bandwidth high-fast serial peripheral interface (SPI). We port the boot loader and device drivers to the implemented board, and construct the firmware development environment for the application programming. The performance of the entire implemented system is demonstrated by analog-digital signal processing tests, and is verified by comparing the test results with those of existing similar systems.

Effect of Microdiversity and Macrodiversity on Average Bit Error Probability in Shadowed Fading Channels in the Presence of Interference

  • Panajotovic, Aleksandra S.;Stefanovic, Mihajlo C.;Draca, Dragan Lj.
    • ETRI Journal
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    • v.31 no.5
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    • pp.500-505
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    • 2009
  • The detrimental effect of short-term fading and shadowing can be mitigated using microdiversity and macrodiversity systems, respectively. In this paper, implementation of selection combining at both micro and macro levels to improve system performance is analyzed. An assessment of the performance of such a system is carried out by considering the desired signal as Rician fading with lognormal shadowing and cochannel interference signal as Rayleigh fading superimposed over lognormal shadowing. The proposed analysis is complemented by various performance evaluation results, including the effects on overall system performance of fading severity, shadowing spreads and branch correlation existing at the base station, and correlation between base stations.

An Energy-Efficient 64-bit Prefix Adder based on Semidynamic and Bypassing Structures

  • Hwang, Jaemin;Choi, Seongrim;Nam, Byeong-Gyu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.1
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    • pp.150-153
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    • 2015
  • An energy-efficient 64-bit prefix adder is proposed for micro-server processors based on both semidynamic and bypassing structures. Prefix adders consist of three main stages i.e. propagate-generate (PG) stage, carry merge (CM) tree, and sum generators. In this architecture, the PG and CM stages consume most of the power because these are based on domino circuits. This letter proposes a semidynamic PG stage for its energy-efficiency. In addition, we adopt the bypassing structure on the CM tree to reduce its switching activity. Experimental results show 19.1% improvement of energy efficiency from prior art.

A study on Development of 300m Class Underwater ROV (300m급 수중ROV 개발에 관한 연구)

  • 이종식;이판묵;홍석원
    • Journal of Ocean Engineering and Technology
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    • v.8 no.1
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    • pp.50-61
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    • 1994
  • A 300 meter class ROV(CROV300) is composed of three parts : a surface unit, a tether cable and an underwater vehicle. The vehicle controller is based on two processors : an Intel 8097-16-bit one chip micro-processor and a Texas Instruments TMS320E25 digital signal processor. In this paper, the surface controller, the vehicle controller and peripheral devices interfaced with the processors are described. These controllers transmit/receive measured status data and control commands through RS422 serial communication. Depth, heading, trimming, camera tilting, and leakage signals are acquired through the embedded AD converters of the 8097. On the other hand, altitude of ROV and lbstacle avoidance signals are processed by the DSP processor and periodically fetched by the 8097. The processor is interfaced with a 4-channel 12-bit D/A converter to generate control signals for DC motors an dseveral transistors to handle the relays for on/off switching of external devices.

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Implementation of Bio-information Sensing System using RF Communication (RF 통신을 이용한 동물 생체정보 센싱 시스템 개발)

  • Seo, Yong-Bae;Chung, Joong-Soo
    • Proceedings of the Korea Contents Association Conference
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    • 2009.05a
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    • pp.1180-1185
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    • 2009
  • Database is constructed according to the development of information contents technology. But the construction of database using bio-information has not been developed. because it is difficult to collect bio-information. This paper presents how to construct database about sensing temperature and tilt of cow based on bio-information using RF communication. The system consists of 8bit micro-controller, tilt sensor, temperature sensor and RF module.

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Obstacle Avoidance and Playing Soccer in a Quadruped Walking Robot (4족 보행 로봇의 장애물 회피와 축구하기)

  • Seo, Hyeon-Se;Sung, Young Whee
    • IEMEK Journal of Embedded Systems and Applications
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    • v.7 no.3
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    • pp.143-150
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    • 2012
  • In this paper, we introduce an intelligent quadruped walking robot that can perform stable walking and a couple of intelligent behaviors. The developed robot has two sets of ultrasonic sensors and six sets of infrared sensors and can perform obstacle avoidance by detecting obstacles and estimating the distances and directions of those obstacles. The robot also has a stereo camera and can paly soccer by detecting a ball and estimating the 3 dimensional coordinates of the ball. In performing those intelligent behaviors, the robot needs to have the capability of generating its walking patterns, solving the inverse kinematics problem, and interfacing several sensors in realtime. Therefore we designed a hierarchical controller that consists of a main controller and an auxiliary controller. The main controller is a 32-bit DSP that can perform fast floating-point opertaion and the auxiliary one is a 8-bit micro-controller. We showed that the developed quadruped walking robot successfully perform those intelligent behaviors through experiments.

A design of 16-bit adiabatic Microprocessor core

  • Youngjoon Shin;Lee, Hanseung;Yong Moon;Lee, Chanho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.3 no.4
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    • pp.194-198
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    • 2003
  • A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

A Study on the Simultaneous Control of Buck and Boost DC-DC Converter by Digital Controller (디지털 제어기에 의한 강압형 및 승압형 DC-DC 컨버터의 동시제어)

  • Park, Hyo-Sik;Kim, Hee-Jun
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.50 no.3
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    • pp.141-146
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    • 2001
  • This paper presents a one digital controller two topology PWM DC-DC converter that controls, simultaneously, the separate Buck converter and boost converter with the different specification by using an inexpensive and efficient 8 bit micro-controller. One timer interrupt is used for the detection of output feedback voltage, and other two timer interrupts are used for the generation of PWM waveform for Buck and Boost converter. The control characteristics of one digital controller two topology PWM DC-DC converter is validated by experimental results.

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On the design of 64bit CLSA adder using the optimized algorithm (최적 알고리즘을 이용한 64비트 CLSA 가산기 설계)

  • 이영훈;김상수
    • Journal of the Korea Society of Computer and Information
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    • v.4 no.3
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    • pp.47-52
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    • 1999
  • The efficiency of an adder which plays an important role in micro-process and DSP greatly depends on the kinds of carry generation method. So in this paper. I used both CLA excellent in the speed and CSA best in the chip-size. The 64bit adder is designed with high speed which is two optimum combination. Therefore this paper suggested the way of CLSA improving both speed and chip-size. and proved the excellence of the designed circuit.

Design of Embedded Platform based on Android (안드로이드 기반 임베디드 플랫폼 설계)

  • Yoon, Chan-Ho;Kim, Gwang-Jun;Jang, Chang-Soo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.10
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    • pp.1545-1552
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    • 2013
  • This paper presents an implementation of embedded platform based ARM A8-cortex processor for android supporting. The development board for S5PV210 is a platform that is suitable for code development of SAMSUNG's S5PV210 32bit RICS micro controller(ARMv7) architecture for hand-held device and general applications. Embedded platform development board offers various function and high efficiencies. In addition to the high performance, the embedded platform offers low current consumption, ensuring low costs and power.