• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.363-363
• /
• 2014

Ruthenium (Ru) has attractive material properties due to its promising characteristics such as a low resistivity ($7.1{\mu}{\Omega}{\cdot}cm$ in the bulk), a high work function of 4.7 eV, and feasibility for the dry etch process. These properties make Ru films appropriate for various applications in the state-of-art semiconductor device technologies. Thus, it has been widely investigated as an electrode for capacitor in the dynamic random access memory (DRAM), a metal gate for metal-oxide semiconductor field effect transistor (MOSFET), and a seed layer for Cu metallization. Due to the continuous shrinkage of microelectronic devices, better deposition processes for Ru thin films are critically required with excellent step coverages in high aspect ratio (AR) structures. In these respects, atomic layer deposition (ALD) is a viable solution for preparing Ru thin films because it enables atomic-scale control of the film thickness with excellent conformality. A recent investigation reported that the nucleation of ALD-Ru film was enhanced considerably by using a zero-valent metallorganic precursor, compared to the utilization of precursors with higher metal valences. In this study, we will present our research results on the synthesis and characterization of novel ruthenium complexes. The ruthenium compounds were easy synthesized by the reaction of ruthenium halide with appropriate organic ligands in protic solvent, and characterized by NMR, elemental analysis and thermogravimetric analysis. The molecular structures of the complexes were studied by single crystal diffraction. ALD of Ru film was demonstrated using the new Ru metallorganic precursor and O2 as the Ru source and reactant, respectively, at the deposition temperatures of $300-350^{\circ}C$. Self-limited reaction behavior was observed as increasing Ru precursor and O2 pulse time, suggesting that newly developed Ru precursor is applicable for ALD process. Detailed discussions on the chemical and structural properties of Ru thin films as well as its growth behavior using new Ru precursor will be also presented.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.377-377
• /
• 2012

Microprocessor technology now relies on copper for most of its electrical interconnections. Because of the high diffusivity of copper, Atomic layer deposition (ALD) $TaN_x$ is used as a diffusion barrier to prevent copper diffusion into the Si or $SiO_2$. Another problem with copper is that it has weak adhesion to most materials. Strong adhesion to copper is an essential characteristic for the new barrier layer because copper films prepared by electroplating peel off easily in the damascene process. Thus adhesion-enhancing layer of cobalt is placed between the $TaN_x$ and the copper. Because, cobalt has strong adhesion to the copper layer and possible seedless electro-plating of copper. Until now, metal film has generally been deposited by physical vapor deposition. However, one draw-back of this method is poor step coverage in applications of ultralarge-scale integration metallization technology. Metal organic chemical vapor deposition (MOCVD) is a good approach to address this problem. In addition, the MOCVD method has several advantages, such as conformal coverage, uniform deposition over large substrate areas and less substrate damage. For this reasons, cobalt films have been studied using MOCVD and various metal-organic precursors. In this study, we used $C_{12}H_{10}O_6(Co)_2$ (dicobalt hexacarbonyl tert-butylacetylene, CCTBA) as a cobalt precursor because of its high vapor pressure and volatility, a liquid state and its excellent thermal stability under normal conditions. Furthermore, the cobalt film was also deposited at various $H_2/NH_3$ gas ratio(1, 1:1,2,6,8) producing pure cobalt thin films with excellent conformality. Compared to MOCVD cobalt using $H_2$ gas as a reactant, the cobalt thin film deposited by MOCVD using $H_2$ with $NH_3$ showed a low roughness, a low resistivity, and a low carbon impurity. It was found that Co/$TaN_x$ film can achieve a low resistivity of $90{\mu}{\Omega}-cm$, a low root-mean-square roughness of 0.97 nm at a growth temperature of $150^{\circ}C$ and a low carbon impurity of 4~6% carbon concentration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.8
• /
• pp.461-465
• /
• 2016

n-type silicon shows the better tolerance towards metal impurities with a higher minority carrier lifetime compared to p-type silicon substrate. Due to better lifetime stability as compared to p-type during illumination made the photovoltaic community to switch toward n-type wafers for high efficiency silicon solar cells. We fabricated the front electrode of the n-type solar cell with AgAl paste. The electrodes characteristics of the AgAl paste depend on the contact junction depth that is closely related to the firing temperature. Metal contact depth with p+ emitter, with optimized depth is important as it influence the resistance. In this study, we optimize the firing condition for the effective formation of the metal depth by varying the firing condition. The firing was carried out at temperatures below $670^{\circ}C$ with low contact depth and high contact resistance. It was noted that the contact resistance was reduced with the increase of firing temperature. The contact resistance of $5.99m{\Omega}cm^2$ was shown for the optimum firing temperature of $865^{\circ}C$. Over $900^{\circ}C$, contact junction is bonded to the Si through the emitter, resulting the contact resistance to shunt. we obtained photovoltaic parameter such as fill factor of 76.68%, short-circuit current of $40.2mA/cm^2$, open-circuit voltage of 620 mV and convert efficiency of 19.11%.

• Journal of the Semiconductor & Display Technology
• /
• v.6 no.3
• /
• pp.19-23
• /
• 2007

The NiSi is very promising candidate for the metallization in 45 nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25\;{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5\;{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process temperature window for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5\;{\Omega}/{\square}$ and $3\;{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

• Korean Journal of Materials Research
• /
• v.9 no.10
• /
• pp.1012-1017
• /
• 1999

Low resistance ohmic contacts to the Si-doped $\textrm{In}_{0.17}\textrm{Ga}_{0.83}\textrm{N}$(~$\times10^{19}\textrm{cm}^{-3}$) were obtained using the W metallization schemes. Specific contact resistance decreased with increasing annealing temperature. The lowest resistance is obtained after a nitrogen ambient annealing at $950^{\circ}C$ for 90 s, which results in a specific contact resistance of $2.75\times10^{-8}\Omega\textrm{cm}^{-3}$. Interfacial reactions and surface are analyzed using x-ray diffraction and scanning electron microscopy (SEM). The X-ray diffraction results show that the reactions between the W film and the $\textrm{In}_{0.17}\textrm{Ga}_{0.83}\textrm{N}$ produce a $\beta$-$W_2N$ phase at the interface. The SEM result shows that the morphology of the contacts is stable up to a temperature as high as $850^{\circ}C$. Possible mechanisms are proposed to describe the annealing temperature dependence of the specific contact resistance.

• Korean Chemical Engineering Research
• /
• v.53 no.4
• /
• pp.517-523
• /
• 2015

As the aluminum (Al) metallization process was replaced with copper (Cu), the damascene process was introduced, which required the planarization step to eliminate over-deposited Cu with Chemical Mechanical Polishing (CMP) process. In this study, the verification of the corrosion inhibitors, one of the Cu CMP slurry components, was conducted to find out the tendency regarding the carboxyl and amino functional group in neutral environment. Through the results of etch rate, removal rate, and chemical ability of corrosion inhibitors based on 1H-1,2,4-triazole as the base-corrosion inhibitor, while the amine functional group presents high Cu etching ability, carboxyl functional group shows lower Cu etching ability than base-corrosion inhibitor which means that it increases passivation effect by making strong passivation layer. It implies that the corrosion inhibitor with amine functional group was proper to apply for 1st Cu CMP slurry owing to the high etch rate and with carboxyl functional group was favorable for the 2nd Cu CMP slurry due to the high Cu removal rate/dissolution rate ratio.

• Solar Energy
• /
• v.17 no.4
• /
• pp.3-11
• /
• 1997

Because grain boundaries in polycrystalline silicon act as potential barriers and recombination centers for the photo-generated charge carriers, these defects degrade conversion effiency of solar cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatment, various grid pattern, selective wet etching for grain boundaries, buried contact metallization along grain boundaries, grid on metallic thin film. Pretreatment above $900^{\circ}C$ in $N_2$ atmosphere, gettering by $POCl_3$ and Al treatment for back surface field contributed to obtain a high quality poly-Si. To prevent carrier losses at the grain boundaries, we carried out surface treatment using Schimmel etchant. This etchant delineated grain boundaries of $10{\mu}m$ depth as well as surface texturing effect. A metal AI diffusion into grain boundaries on rear side reduced back surface recombination effects at grain boundaries. A combination of fine grid with finger spacing of 0.4mm and buried electrode along grain boundaries improved short circuit current density of solar cell. A ultra-thin Chromium layer of 20nm with transmittance of 80% reduced series resistance. This paper focused on the grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency.

• Corrosion Science and Technology
• /
• v.9 no.6
• /
• pp.276-280
• /
• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

• Korean Journal of Materials Research
• /
• v.11 no.6
• /
• pp.527-532
• /
• 2001

Dry etching of copper film using $O_2$ plasma and H(hfac) has been investigated. A one-step process consisting of copper film oxidation with an $O_2$ plasma and the removal of surface copper oxide by the reaction with H(hfac) to form volatile Cu(hfac)$_2$ and $H_2O$ was carried but. The etching rate of Cu in the range from 50 to 700 /min was obtained depending on the substrate temperature, the H(hfac)/O$_2$ flow rate ratio, and the plasma power. The copper film etch rate increased with increasing RF power at the temperatures higher than 215$^{\circ}C$. The optimum H(hfac)/O$_2$ flow rate ratio was 1:1, suggesting that the oxidation process and the reaction with H(hfac) should be in balance. Cu patterning using a Ti mask was performed at a flow rate ratio of 1:1 on 25$0^{\circ}C$\ulcorner and an isotropic etching profile with a taper slope of 30$^{\circ}$was obtained. Cu dry patterning with a tapered angle which is necessary for the advanced high resolution large area thin film transistor liquid-crystal displays was thus successfully obtained from one step process by manipulating the substrate temperature, RF power, and flow rate ratio.

• Journal of the Microelectronics and Packaging Society
• /
• v.6 no.4
• /
• pp.1-7
• /
• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.