• Journal of IKEEE
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• v.26 no.2
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• pp.306-312
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• 2022

We investigated electrical properties and deep level traps in 4H-SiC merged PiN Schottky (MPS) diodes with different barrier heights by different PN ratios and metallization annealing temperatures. The barrier heights of MPS diodes were obtained in IV and CV characteristics. The leakage current increased with the lowering barrier height, resulting in 10 times larger current. Additionally, the deep level traps (Z_1/2 and RD_1/2) were revealed by deep level transient spectroscopy (DLTS) measurement in four MPS diodes. Based on DLTS results, the trap energy levels were found to be shallow level by 22~28% with lower barrier height It could confirm the dependence of the defect level and concentration determined by DLTS on the Schottky barrier height and may lead to incorrect results regarding deep level trap parameters with small barrier heights.

• Nuclear Engineering and Technology
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• v.54 no.10
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• pp.3841-3848
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• 2022

The effect of modifiers on the optical features and radiation defying ability of the Eu³⁺ ions doped multi constituent glasses was examined. XRD has established the amorphous nature of the specimen. The presence of various functional/fundamental groups in the present glasses was analyzed through FTIR spectra. The physical, structural and elastic traits of the glasses were explored. The variation in the structural compactness of the glass structure according to the incorporated modifier was enlightened to describe their suitability for a better shielding media. For the examined glasses, the metallization criterion value varied in the range 0.613-0.692, indicating the non-metallic character of the glasses with possible nonlinear optical applications. The computed elastic moduli expose the Li-containing glass (BTLi:Eu) to be tightly packed and rigid, which is a requirement for a better shielding channel. Furthermore, the optical bandgap and the Urbach energy values are calculated based on the optical absorption spectra. The evaluated bonding parameters revealed the nature of the fabricated glasses covalent. In addition, we investigated the radiation attenuation attributes of the prepared Eu³⁺ ions doped multi constituent glasses using Phy-X software. We determined the linear attenuation coefficient (LAC) and reported the influence of the five oxides Li₂O₃, CaO, BaO, SrO, and ZnO on the LAC values. The LAC varied between 0.433 and 0.549 cm^-1 at 0.284 MeV. The 39B₂O₃-25TeO₂-15Li₂O₃-10Na₂O-10K₂O-1Eu₂O₃ glass has a much smaller LAC than the other glasses.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.3 s.32
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• pp.37-45
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• 2004

Electroless Ni(P) has been widely used for under bump metallization (UBM) of flip chip and surface finish layer in microelectronic packaging because of its excellent solderability, corrosion resistance, uniformity, selective deposition without photo-lithography, and also good diffusion barrier. However, the brittle fracture at solder joints and the spatting of intermetallic compound (IMC) associated with electroless Ni(P) are critical issues for its successful applications. In the present study, the mechanism of IMC spatting and microstructure change of the Ni(P) film were investigated with varying P content in the Ni(P) film (4.6,9, and $13 wt.\%$P). A reaction between Sn penetrated through the channels among $Ni_3Sn_4$ IMCs and the P-rich layer ($Ni_3P$) of the Ni(P) film formed a $Ni_3SnP$ layer. Thickening of the $Ni_3SnP$ layer led to $Ni_3Sn_4$ spatting. After $Ni_3Sn_4$ spatting, the Ni(P) film directly contacted the molten solder and the $Ni_3P$ phase further transformed into a $Ni_2P$ phase. During the crystallization process, some cracks formed in the Ni(P) film to release tensile stress accumulated from volume shrinkage of the film.

• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.161-166
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• 2007

Photovoltaic (PV) technology permits the transformation of solar light directly into electricity. For the last five years, the photovoltaic sector has experienced one of the highest growth rates worldwide (over 30% in 2006) and for the next 20 years, the average production growth rate is estimated to be between 27% and 34% annually. Currently the cost of electricity produced using photovoltaic technology is above that for traditional energy sources, but this is expected to fall with technological progress and more efficient production processes. A large scale production of solar grade silicon material of high purity could supply the world demand at a reasonably lower cost. A shift from crystalline silicon to thin film is expected in the future. The technical limit for the conversion efficiency is about 30%. It is assumed that in 2030 thin films will have a major market share (90%) and the share of crystalline cells will have decreased to 10%. Our research at Sungkyunkwan University of South Korea is confined to crystalline silicon solar cell technology. We aim to develop a technology for low cost production of high efficiency silicon solar cell. We have successfully fabricated silicon solar cells of efficiency more than 16% starting with multicrystalline wafers and that of efficiency more than 17% on single crystalline wafers with screen printing metallization. The process of transformation from the first generation to second generation solar cell should be geared up with the entry of new approaches but still silicon seems to remain as the major material for solar cells for many years to come. Local barriers to the implementation of this technology may also keep continuing up to year 2010 and by that time the cost of the solar cell generated power is expected to be 60 cent per watt. Photovoltaic source could establish itself as a clean and sustainable energy alternate to the ever depleting and polluting non-renewable energy resource.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.228-238
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• 1992

An investigation on the step-coverage of PECVD and $O_3$ ThCVD oxides was undertaken to implement into the void-free inter metal dielectric planarization using multi-chamber system for the submicron double level metallization. At various initial aspect ratios the instantaneous aspect ratios were measured through modelling and experiment by depositing the oxides up to $0.9{\mu}m$ in thickness in order to monitor the onset of void formation. The modelling was found to be in a good agreement with the observed instantaneous aspect ratio of TEOS-based PECVD oxide whose re-entrant angle was less than $5^{\circ}$. It is demonstrated that either keeping the instantaneous aspect ratio of PECVD oxide as a first layer less than a factor of 0.8 or employing Ar sputter etch to create sloped oxide edge ensures the void-free planarization after$O_3$ ThCVD oxide deposition whose step-coverage is superior to PECVD oxide. It has been observed that $O_3$ ThCVD oxide etchback scheme has shown higher yield of via contact chain than non etchback process, with resistance per via contact of $0.1~0.3{\Omega}/{\mu}m^2$.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.1 s.34
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• pp.41-46
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• 2005

A systematic investigation of shear testing was conducted to find a relationship between Ni-Sn intermetallic spatting and the brittle fracture observed in electroless Ni(P)/solder interconnection. Brittle fracture was found in the solder joints made of Sn-3.5Ag, while only ductile fracture was observed in a Cu-containing solder (Sn-3.0Ag-0.5Cu). For Sn-3.0Ag-0.5Cu joints, $(Ni,Cu)_3Sn_4$ and/or $(Cu,Ni)_6Sn_5$ compound were formed at the interface without spatting from the Ni(P) film. For Sn-3.5Ag, $Ni_3Sn_4$ compound was formed and brittle fracture occurred in solder pads where $Ni_3Sn_4$ had spalled. From the analysis of fractured surfaces, it was found that the brittle fracture occurs through the $Ni_3SnP$ layer formed between $Ni_3Sn_4$ intermetallic layer and the Ni(P) film. Since the $Ni_3SnP$ layer is getting thicker during/ after $Ni_3Sn_4$ spatting, suppression of $Ni_3Sn_4$ spatting is crucial to ensure the reliability of Ni(P)/solder system.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.197-205
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• 2005

Development of the packaging is one of the critical issues for commercialization of the RF-MEMS devices. RF MEMS package should be designed to have small size, hermetic protection, good RF performance and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at the temperature below $300{\times}C$ is used. Au-Sn multilayer metallization with a square loop of $70{\mu}m$ in width is performed. The electrical feed-through is achieved by the vertical through-hole via filled with electroplated Cu. The size of the MEMS Package is $1mm\times1mm\times700{\mu}m$. By applying $O_2$ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface as well as via hole. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.23-29
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• 2006

Ultrasonic soldering of Si-wafer to FR-4 PCB at ambient temperature was investigated. The UBM of Si-substrate was Cu/ Ni/ Al from top to bottom with thickness of $0.4{\mu}m,\;0.4{\mu}m$, and $0.3{\mu}m$ respectively. The pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom with thickness of $0.05{\mu}m,\;5{\mu}m$, and $18{\mu}m$ respectively. Sn-3.5wt%Ag foil rolled to $100{\mu}m$ was used for solder. The ultrasonic soldering time was varied from 0.5 s to 3.0 s and the ultrasonic power was 1,400 W. The experimental results show that a reliable bond by ultrasonic soldering at ambient temperature was obtained. The shear strength increased with soldering time up to a maximum of 65 N at 2.5 s. The strength decreased to 34 N at 3.0 s because cracks were generated along the intermetallic compound between Si-wafer and Sn-3.5wt%Ag solder. The Intermetallic compound produced by ultrasonic soldering between the Si-wafer and the solder was $(Cu,Ni)_{6}Sn_{5}$.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.43-49
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• 2010

Direct printing technology is an attractive metallization method, which has become immerging as "Green technology" to the conventional photolithography, on account of low cost, simple process and environment-friendliness. In order to commercialize the printed electronics in industry, it is essential to evaluate the electrical properties of conductive circuits using direct printing technology. In this contribution, we focused on the electrical characteristics of inkjet-printed circuits. A Cu nanoink was inkjet-printed onto a Bisaleimide triazine(BT) substrate with parallel transmission line(PTL) and coplanar waveguide(CPW) type, then was sintered at $250^{\circ}C$ for 30 min. We calculated the resistivity of printed circuits through direct current resistance by the measurement of I-V curve: the resistivity was approximately 0.558 ${\mu}{\Omega}{\cdot}cm$ which is about 3.3 times that of bulk Cu. Cascade's probe system in the frequency range from 0 to 30 GHz were employed to measure the Scattering parameter(S-parameter) with or without a gap between the substrate and the probe station chuck. The result of measured S-parameter showed that all printed circuits had over 5 dB of return loss in the entire frequency range. In the curve of insertion loss, $S_{21}$, showed that the PTL type circuits had better transmission of radio frequency (RF) than CPW type.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.1 no.2
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• pp.79-93
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• 1991

With the advent of ULSI, many problems in previous metallization techniques and interconnection materials have become more serious. In this work, selective deposition of copper to fill the submicron contact has been tried. After forming electro-deposited copper films on p-type (100) silicon wafer using 0.75M $CuSO_4{\cdot}$5H_2O$ as an electrolyte, the effect of deposition time, current density and concentration of an additive on film properties were investigated. Film thickness, particle size and resistivity were analyzed by Alpha Step, SEM and 4 - point probe measurement respectively. The deposition rate was about $0.5-0.6\mu\textrm{m}$/min at $2A/dm^2$ and the particle size increased with increasing current density. The resistivities of electro-deposited copper films were about $3-6{\mu}{\Omega}{\cdot}$cm for the particle size above $4000{\AA}$. By the addition of 0.2 g/l gelatin, the particle size was reduced to less than $0.1{\mu}m $ and selective plugging of copper on submicron contacts could be successfully achieved.