• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.140-150
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• 1995

A symbolic layout generator, called Flexible Module Generator (FMG), has been developed for transgorming a given CMOS circuit netlist into an optimized symbolic layout. Contrary to other conventional module generators which place transistors either in horizontal or in vertical direction, FMG places transittors in any hence can multiples of 90$^{\circ}$. This flexible layout style can maximize the diffusion sharing and hence can reduce the wire-length for both of area minimization and performance improvement. In FMG, transistors are initially randomly placed and then selected transistors are iteratively replaced using an optimization technique based on simulated evolution. Whenever a transistor is replaced, the affected nets are rerouted. Constraints on the shape, aspect ratio, and critical path delays are considered during the optimization process. Routing is performed by using a modified maze router on polysilicon, metal 1, and metal 2 interconnection layers. additional routing grids are added, if necessary, for complete routing. Unused rows or columns are removed after routing for area minimization. Experimental reasults show that FMG synthesizes satisfactory layouts.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.81-82
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• 2006

Chemical mechanical polishing (CMP) technology has been widely used for global planarization of multi-level interconnection for ULSI applications. However, the cost of ownership and cost of consumables are relatively high because of expensive slurry. In this paper, so as to investigate the influence of mixed abrasive slurry (MAS), such as $ZrO_2$, $CeO_2$, and $MnO_2$ for Ti-CMP application.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.587-590
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• 2000

This paper presents the characteristics of metal thin-film pressure sensors. The micro pressure sensors consists of a chrom thin-film, patterned on a Wheatstone bridge configuration, sputter-deposited onto thermally oxidized Si wafer an aluminium interconnection layer. The fabricated micro pressure sensors shows a low temperature coefficient of resistance, high-sensitivity, low non-linearity and excellent temperature stability. The sensitivity is 1.16~1.21 mV/V.kgf/$\textrm{cm}^2$ in the temperature range of 25~l0$0^{\circ}C$ and the maximum non-linearity is 0.21 %FS.

• Journal of the Korean Electrochemical Society
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• v.10 no.2
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• pp.94-103
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• 2007

The transition of interconnection metal from aluminum alloy to copper has been introduced to meet the requirements of high speed, ultra-large scale integration, and high reliability of the semiconductor device. Since copper, which has low electrical resistivity and high resistance to degradation, has different electrical and material characteristics compared to aluminum alloy, new related materials and processes are needed to successfully fabricate the copper interconnection. In this review, some important factors of multilevel copper damascene process have been surveyed such as diffusion barrier, seed layer, organic additives for bottom-up electro/electroless deposition, chemical mechanical polishing, and capping layer to introduce the related issues and recent research trends on them.

• Korean Journal of Materials Research
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• v.9 no.2
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• pp.124-131
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• 1999

Copper film, which is expected to be used as interconnection material for 1 giga DRAM integrated circuits was deposited on hole and trench patterns by Metal Organic Chemical Vapor Deposition(MOCVD) method. After a reflow process, contact and L/S patterns were filled by copper and the characteristics of the Cu reflow process were investigated. When deposited Cu films were reflowed, grain growth and agglomeration of Cu have occurred in surfaces and inner parts of patterns as well as complete filling in patterns. Also Cu thin oxide layers were formed on the surface of Cu films reflowed in $O_2$ambient. Agglomeration and oxidation of Cu had bad influence on the electrical properties of Cu films especially, therefore, their removal and prevention were studied simultaneously. As a pattern size is decreased, preferential reflow takes place inside the patterns and this makes advantages in filling patterns of deep submicron size completely. With Cu reflow process, we could fill the patterns with the size of deep sub-micron and it is expected that Cu reflow process could meet the conditions of excellent interconnection for 1 giga DRAM device when it is combined with Cu MOCVD and CMP process.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.5
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• pp.94-100
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• 1994

The junction failure mechanism of W plugs has not been fully understood while the selective W deposition has been widely used for plugging interconnection lines. In this paper, the thermal stability and junction failure mechanism of sub-micron contacts using selective CVD-W plugs were intensively studied with the metal lines of AISiCu, Ti/AISiCu and TiN/AISiCu. The experimental results showed that the contact chain resistance and leakage current in the AISiCu and Ti/AISiCu metallizations were significantly degraded after annealing. From the SEM analysis, it was found that the junction spiking, due to the Al atoms diffusion along the porous interface between selective CVD-W and contactside wall, caused the junction failure. In constast, there was no degradation of the contact resistance and junction leakage current in TiN/AISiCu metal structu-re. It is believed that the TiN barrier layer could prevent AI(Ti) atoms Fromdiffusing. Therefore, TiN barrier between W plug and Al should be used to impro-ve the thermal stability of sub-micron contacts using the selective CVD-W plugs.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.9
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• pp.104-113
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• 1994

We have fabricated n-p-n HBTs using 3-inchAlgaAs/GaAs hetero structure epi-wafers grown by MBE. DC and AC characteristics of HBT devices were measured and analyzed. For HBT epi-structure, Al composition of emitter was graded in the region between emitter cap and emitter. And base layer was designed with concentration of 1${\times}10^{19}/cm^{3}$ and thickness of 50nm, and Be was used as the p-type dopant. Principal processes for device fabrication consist of photolithography using i-line stepper, wet mesa etching, and lift-off of each ohmic metal. The PECVD SiN film was used as the inslator for the metal interconnection. HBT device with emitter size of 3${\times}10{\mu}m^{2}$ resulted in cut-off frequency of 35GHz, maximum oscillation frequency of 21GHz, and current gain of 60. The distribution of the ideality factor of collector and base current was very uniform, and the average values of off-set voltage and current was very uniform, and the average values of off-set voltage and current gain were 0.32V and 32 within a 3-inch wafer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.6
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• pp.515-520
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• 2005

CMP(chemical mechanical polishing) process has been attracted as an essential technology of multi-level interconnection. Also CMP process got into key process for global planarization in the chip manufacturing process. In this study, potentiodynamic polarization was carried out to investigate the influences of $H_2O_2$ concentration and metal oxide formation through the passivation on tungsten and titanium. Fortunately, the electrochemical behaviors of tungsten and titanium are similar, an one may expect. As an experimental result, electrochemical corrosion of the $5\;vol\%\;H_2O_2$ concentration of tungsten and titanium films was higher than the other concentrations. According to the analysis, the oxidation state and microstructure of surface layer were strongly influenced by different oxidizer concentration. Moreover, the oxidation kinetics and resulting chemical state of oxide layer played critical roles in determining the overall CMP performance. Therefore, we conclude that the CMP characteristics tungsten and titanium metal layer including surface roughness were strongly dependent on the amounts of hydrogen peroxide oxidizer.