• Design & Manufacturing
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• v.14 no.1
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• pp.1-7
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• 2020

In this study, the variation of the shrinkage in the thickness direction of the molded parts according to the gate size of the polymer core fabricated through the 3D printer using the SLS method was studied. The polymer cores are laser sintered and the powder material is nylon base PA2200. The polymer cores have lower heat transfer rate and rigidity than the metal core due to the characteristics of the material. Therefore, the injection molding test conditions are set to minimize the deformation of the core during the injection process. The resin used in the injection molding test is a PP material. The packing condition was set to 80, 90 and 100% of the maximum injection pressure for each gate size. The runner diameter used was ∅3mm, and the gates were fabricated in semicircle shapes with cross sections 1, 2, and 3 ㎟, respectively. Thickness measurement was performed for 10 points at 2.5 mm intervals from the point 2.5 mm away from the gate, and the shrinkage to thickness was measured for each point. The shrinkage rate according to the gate size tends to decrease as the cross-sectional area decreases as the maximum injection pressure increases. The average thickness shrinkage rate was close to 0% when the packing pressure was 90% for the gate area of 1mm2. When the holding pressure was set to 100%, the shrinkage was found to decrease by 3% from the standard dimension due to the over-packing phenomenon. Therefore, the smaller the gate, the more closely the molded dimensions can be molded due to the high pressure generation. It was confirmed that precise packing process control is necessary because over-packing phenomenon may occur.

• Journal of the korean society of oceanography
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• v.35 no.2
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• pp.89-97
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• 2000

The pyritization of heavy metals in Lake Shihwa sediments was investigated to determine sedimentary Pyrite-heavy metal associations influenced by various metal fractions, organic carbon, and total reduced sulfur. Parameters indicating the degree of heavy metal pyritization (DTMP) and degree of pyritization (DOP) were used to study the incorporation of heavy metals into the pyrite phase. The DOP levels ranged from 3.28-39.45%, showing wide differences among sampling stations. The levels were greater near the water gate and the center of the lake than near the industrial complex. The spatial pattern of the DOP levels was similar to the S/C ratio and also to the salinity. Based on the measured relationships between DOP and DTMP, heavy metals can be divided into three groups. In the first group was As, which showed a high affinity for pyrite. In the second group were Ni, Co and Cu, which showed a gradual increase in DTMP with increasing DOP. In the final group were Pb, Zn, Mn and Cr, which all showed a low DTMP with constant values with respect to DOP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.45-49
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• 2001

We have investigated physical and electrical properties of the Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin film for alternative gate dielectrics in the metal-oxide-semiconductor device. The oxidation of Hf deposited directly on the Si substrate results in the H $f_{x}$/ $O_{y}$ interfacial layer and the high-k Hf $O_2$film simultaneously. Interestingly, the post-oxidation N2 annealing of the H102/H1Si70y thin films reduces(increases) the thickness of an amorphous HfS $i_{x}$/ $O_{y}$ layer(Hf $O_2$ layer). This phenomenon causes the increase of the effective dielectric constant, while maintaining the excellent interfacial properties. The hysteresis window in C-V curves and the midgap interface state density( $D_{itm}$) of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ thin films less than 10 mV and ~3$\times$10$^{11}$ c $m^{-2}$ -eV without post-metallization annealing, respectively. The leakage current was also low (1$\times$10-s A/c $m^2$ at $V_{g}$ = +2 V). It is believed that these excellent results were obtained due to existence of the amorphous HfS $i_{x}$/ $O_{y}$ buffer layer. We also investigated the charge trapping characteristics using Fowler-Nordheim electron injection: We found that the degradation of Hf $O_2$/HfS $i_{x}$/ $O_{y}$ gate oxides is more severe when electrons were injected from the gate electrode.e electrode.e.e electrode.e.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.

• Journal of Power Electronics
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• v.9 no.3
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• pp.464-471
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• 2009

This paper introduces a new Motion-$SPM^{TM}$ (Smart Power Modules) module in Single In-line Package (SIP), which is a fully optimized intelligent integrated IGBT inverter module for up to 1kW low power motor drive applications. This module offers a sophisticated, integrated solution and tremendous design flexibility. It also takes advantage of pliability for the arrangement of heat-sink due to two types of lead forms. It comes to be realized by employing non-punch-through (NPT) IGBT with a fast recovery diode and highly integrated building block, which features built-in HVICs and a gate driver that offers more simplicity and compactness leading to reduced costs and high reliability of the entire system. This module also provides technical advantages such as the optimized cost effective thermal performances through IMS (Insulated Metal Substrate), the high latch immunity. This paper provides an overall description of the Motion-$SPM^{TM}$ in SIP as well as actual application issues such as electrical characteristics, thermal performance, circuit configurations and power ratings.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1288-1290
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• 2005

We report on the structural and electrical properties of amorphous Yttria-stabilized zirconia (YSZ) thin films which are the potential high-k gate dielectric material of organic thin film transistor (OTFT). To investigate the influence of the oxygen flow rate on the structural and electrical properties of the YSZ films, XRD, XPS, J-E, I-V were carried out in this work. Oxygen vacancies are expected to be the most predominant type of defect in metal-oxide dielectrics. The leakage current density decreased mainly because of the reduction of oxygen vacancies with increasing oxygen flow rate.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.278-278
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• 2016

Solution-processed metal-oxide semiconductors have been considered as the next generation semiconducting materials for transparent and flexible electronics due to their high electrical performance. Moreover, since the oxide semiconductors show high sensitivity to light illumination and possess persistent photoconductivity (PPC), these properties can be utilized in realizing optical memory devices, which can transport information much faster than the electrons. In previous works, metal-oxide semiconductors are utilized as a memory device by using the light (i.e. illumination does the "writing", no-gate bias recovery the "reading" operations) [1]. The key issues for realizing the optical memory devices is to have high photoconductivity and a long life time of free electrons in the oxide semiconductors. However, mono-layered indium-zinc-oxide (IZO) and mono-layered indium-gallium-zinc-oxide (IGZO) have limited photoconductivity and relaxation time of 570 nA, 122 sec, 190 nA and 53 sec, respectively. Here, we boosted up the photoconductivity and relaxation time using a double-layered IZO/IGZO active layer structure. Solution-processed IZO (top) and IGZO (bottom) layers are prepared on a Si/SiO2 wafer and we utilized the conventional thermal annealing method. To investigate the photoconductivity and relaxation time, we exposed 9 mW/cm2 intensity light for 30 sec and the decaying behaviors were evaluated. It was found that the double-layered IZO/IGZO showed high photoconductivity and relaxation time of 28 uA and 1048 sec.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.228-238
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• 2002

This paper presents a digital controller of the electronic ballast using high frequency modulation method for the metal halide lamp. The proposed controller includes the control algorithm for soft starting, no load protection, over current protection and power control. The proposed digital controller, moreover, has the high frequency modulation scheme and the tracking algorithm to avoid acoustic resonance phenomena. For the math production with the low cost using the ASICs (Application Specific Integrated Circuit), the proposed digital controller has been designed with the FPGAs(Field Programmable Gate array) only, without any microprocessor. In this paper, the detail digital control algorithms are described and the experimental results of prototype 150w metal halide electronic ballast are presented.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.191-191
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• 2007

유효 산화막 두께가 약 2.0nm 정도의 $ZrO_2$ 절연막 위에 Ta-Mo 금속 합금과 Ru-Zr 금속 합금을 Co-sputtering 방법을 이용하여 여러 가지 일함수를 갖는 MOS capacitor를 제작하여 전기적 재료적 특성에 관하여 연구를 하였다. 그 결과 각각의 금속 합금 게이트는 4.1eV 에서 5.1eV 사이의 다양한 일함수를 나타냈으며, $400^{\circ}C$, $500^{\circ}C$, $600^{\circ}C$, $700^{\circ}C$, $800^{\circ}C$ RTA 후의 C-V특성 곡선 및 I-V 측정을 통하여 누설전류를 확인하였다. 그 결과 Ta-Mo 금속 합금의 경우 스퍼터링 파워가 100W/70W에서 NMOS에 적합한 일함수를 가졌으며, Ru-Zr 금속 합금의 경우 스퍼터링 파워가 50W/100W에서 NMOS에 적합한 일함수를 가졌다. 열처리 후의 C-V특성 곡선에서도 정전용랑 값이 거의 변하지 않았으며 평탄 전압의 변화도 거의 없었다. 누설전류 특성에서는 물리적 두께가 비슷한 기존의 $SiO_2$ 절연막에서 실험결과와 비교하여 약 100배 정도 감소되었음을 알 수 있었다. 또한 기존의 실험들에서 나타난 열처리 후의 $ZrO_2$ 절연막과 Si 기판 사이의 Interfacial layer 의 동반 두께 증가로 인한 전기적 특성 저하가 나타나지 않는 줄은 특성을 보여준다.