• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.389-392
• /
• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and non-uniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between particle size and CMP with particle size analysis of used slurry.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.28 no.11
• /
• pp.1807-1812
• /
• 2004

The application of chemical mechanical polishing(CMP) has a long history. Recently, CMP has been used in the planarization of the interlayer dielectric(ILD) and metal used to form the multilevel interconnections between each layers. Therefore, much research has been conducted to understand the basic mechanism of the CMP process. CMP performed by the down force and the relative speed between pad and wafer with slurry is typical tribo-system. In general, studies have indicated that removal rate is relative to energy. Accordingly, in this study, CMP results will be analyzed by a viewpoint of the friction energy using friction force measurement. The results show that energy would not constant in the same removal rate conditions

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.119-120
• /
• 2008

ILD CMP process has been well accepted for the planarization of the dielectric oxide film and becomes a critical process in ULSI manufacturing due to the rapid shrinkage of the design rule for the device. In total manufacturing process steps for a device, the proportion of ILD CMP process has been gradually increased. Ever since ILD CMP has been introduced, the scratches have been a major defects on polished surfaces which cause the electrical shorts between vias or metal lines [1,2]. It was reported that micro-scratches are caused by large, irregularly shaped particles during CMP process. Therefore, most of the CMP users have used < 5 m POU filter to remove and reduce the scratch source from the slurry. However, the scratch has always been the biggest concern in ILD polishing whatever preventive actions are taken. Silica and ceria slurries are widely used for ILD CMP process. There are not much differences in generated scratches and their formation mechanism. In this study, the scratches were investigated as a function of polishing conditions with possible explanation on formation mechanism in ILD CMP.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.06a
• /
• pp.571-572
• /
• 2006

Tungsten CMP needs interconnect of semiconductor device ULSI chip and metal plug formation, CMP technology is essential indispensable method for local planarization. This Slurry development also for tungsten CMP is important, slurry of metal wiring material that is used present is depending real condition abroad. It is target that this research makes slurry of efficiency that overmatch slurry that is such than existing because focus and use colloidal silica by abrasive particle to internal production technology development. Compared selectivity of slurry that is developed with competitor slurry using 8" tungsten wafer and 8" oxide wafer in this experiment. And removal rate measures about density change of $H_2O_2$ and Fe particle. Also, corrosion potential and current density measure about Fe ion and Fe particle. As a result, selectivity find 83:1, and expressed similar removal rate and corrosion potential and current density value comparing with competitor slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07a
• /
• pp.370-373
• /
• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.20-23
• /
• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• Proceedings of the KSME Conference
• /
• 2003.04a
• /
• pp.1296-1301
• /
• 2003

The chemical mechanical polishing(CMP) is necessarily applied to manufacturing the dielectric layer and metal line in the semiconductor device. The conditioning of polishing pad in CMP process additionally operates for maintaining the removal rate, within wafer non-uniformity, and wafer to wafer non-uniformity. But the fixed abrasive pad(FAP) using the hydrophilic polymer with abrasive that has the swelling characteristic by water owns the self-conditioning advantage as compared with the general CMP. FAP also takes advantage of planarity, resulting from decreasing pattern selectivity and defects such as dishing due to the reduction of abrasive concentration. This paper introduces the manufacturing technique of FAP. And the tungsten CMP using FAP achieved the good conclusion in point of the removal rate, non-uniformity, surface roughness, material selectivity, micro-scratch free contemporary with the pad life-time.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.5 s.98
• /
• pp.40-47
• /
• 1999

In CMP for semiconductor wafer films, the acceptable within-chip planarity, within-wafer and wafer-to-wafer nonuniformity could be achieved by conditioning. The role of conditioning is to remove continuously polishing residues from pad and to maintain the initial pad surface pores. To reach these requirements, the diamond grits disk has been considered as a conventional conditioner. However, we have investigated many defects as scratch on wafers out of diamond grits shedding, contaminations from bonding materials, and pad pore subsidences by over-conditioning. So, this paper studies the effect of ultrasonic vibration in CMP conditioning as a representative. The effect of ultrasonic vibration was certified through ILD, Metal CMP.

• Journal of the Korean Society for Precision Engineering
• /
• v.21 no.7
• /
• pp.22-29
• /
• 2004

As a result of high integration of semiconductor device, the global planarization of multi-layer structures is necessary. So the chemical mechanical polishing(CMP) is widely applied to manufacturing the dielectric layer and metal line in the semiconductor device. CMP process is under influence of polisher, pad, slurry, and process itself, etc. In comparison with the general CMP which uses the slurry including abrasives, fixed abrasive pad takes advantage of planarity, resulting from decreasing pattern selectivity and defects such as dishing & erosion due to the reduction of abrasive concentration especially. This paper introduces the manufacturing technique of fixed abrasive pad using hydrophilic polymers with swelling characteristic in water and explains the self-conditioning phenomenon. And the tungsten CMP using fixed abrasive pad achieved the good conclusion in terms of the removal rate, non-uniformity, surface roughness, material selectivity, micro-scratch free contemporary with the pad life-time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.05c
• /
• pp.149-153
• /
• 2003

Chemical mechanical polishing (CMP) technology for global planarization of multi-level inter-connection structure has been widely studied for the next generation devices. CMP process has been paid attention to planarized pre-metal dielectric (PMD), inter-layer dielectric (ILD) interconnections. Expecially, shallow trench isolation (STI) used to CMP process on essential. Recently, the direct STI-CMP process without the conventional complex reverse moat etch process has established by using slurry additive with the high selectivity between $SiO_2$ and $Si_3N_4$ films for the purpose of process simplification and n-situ end point detection(EPD). However, STI-CMP process has various defects such as nitride residue, tom oxide and damage of silicon active region. To solve these problems, in this paper, we studied the planarization characteristics using a high selectivity slurry(HSS). As our experimental results, it was possible to achieve a global planarization and STI-CMP process could be dramatically simplified. Also we estimated the reliability through the repeated tests with the optimized process conditions in order to identify the reproducibility of HSS STI-CMP process.