• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.6
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• pp.137-145
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• 2010

Digital vessel have to accurate and efficient mange the digital data from various sensors in the digital vessel. But, In sensor network, it is difficult to transmit and analyze the entire stream data depending on limited networks, power and processor. Therefore it is suitable to use alternative stream data processing after classifying the continuous stream data. In this paper, We propose efficient processing method that arrange some sensors (temperature, humidity, lighting, voice) and process query based on sliding window for efficient input stream and pre-clustering using multiple Support Vector Machine(SVM) algorithm and manage hash table to summarized information. Processing performance improve as store and search and memory using hash table and usage reduced so maintain hash table in memory. We obtained to efficient result that accuracy rate and processing performance of proposal method using 35,912 data sets.

• Journal of Power Electronics
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• v.11 no.2
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• pp.228-236
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• 2011

The ${\Delta}\;V_{10}$ or 10-Hz flicker index, as a common method of measurement of voltage flicker severity in power systems, requires a high computational cost and a large amount of memory. In this paper, for measuring the ${\Delta}\;V_{10}$ index, a new method based on the Adaline (adaptive linear neuron) system, the FFT (fast Fourier transform), and the PSO (particle swarm optimization) algorithm is proposed. In this method, for reducing the sampling frequency, calculations are carried out on the envelope of a power system voltage that contains a flicker component. Extracting the envelope of the voltage is implemented by the Adaline system. In addition, in order to increase the accuracy in computing the flicker components, the PSO algorithm is used for reducing the spectral leakage error in the FFT calculations. Therefore, the proposed method has a lower computational cost in FFT computation due to the use of a smaller sampling window. It also requires less memory since it uses the envelope of the power system voltage. Moreover, it shows more accuracy because the PSO algorithm is used in the determination of the flicker frequency and the corresponding amplitude. The sensitivity of the proposed method with respect to the main frequency drift is very low. The proposed algorithm is evaluated by simulations. The validity of the simulations is proven by the implementation of the algorithm with an ARM microcontroller-based digital system. Finally, its function is evaluated with real-time measurements.

• The Journal of the Korea Contents Association
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• v.9 no.11
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• pp.90-99
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• 2009

This paper presents the implementation of RFID EPC global network educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The ATmega128 VLSI chip is used for the processor of the reader and the active tag. As the development environment, AVR compiler is used for the reader and the active tag of which the programming language is C. The visual C++language of the visual studio on the PC activated as the server is used for development language. Main functions of this system are to control tag containing EPC global Data by PC through the reader, to obtain information of tag through the internet and to read/write data on tag memory. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag. Software implementation of 900MHz EPC global RFID educational system is done on the basis of these functions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.73-80
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• 2005

The Turbo decoders based on Log-MAP decoding algorithm inherently requires large amount of memory and intensive complexity of hardware due to iterative decoding, despite of excellent decoding efficiency. To decrease the large amount of memory and reduce hardware complexity, the result of previous research. And this paper design the Turbo decoder applicable to the 3G W-CDMA systems. Through the result of previous research, we decided 5-bits for the received data 6-bits for a priori information, and 7-bits for the quantization state metrics. The error correction term for $MAX^{*}$ operation which is the main function of Log-MAP decoding algorithm is implemented with very small hardware overhead. The proposed Turbo decoder is synthesized in $0.35\mu$m Hynix CMOS technology. The synthesized result for the Turbo decoder shows that it supports a maximum 9Mbps data rate, and a BER of $10^{-6}$ is achieved(Eb/No=1.0dB, 5 iterations, and the interleaver size $\geq$ 2000).

• Journal of The Korean Association of Information Education
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• v.3 no.1
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• pp.86-93
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• 1999

In this paper, we have designed and implemented that PC management system has the function of monitoring and controlling system management MIB defined for PC management using SNMP in PC room. System management MIB consists of monitoring MIB for system and processor information and controlling MIB for backup and restoration. For this, we have added new defined MIB variables to standard MIB and displayed system information, processor information, backup and restoration information of managed PC. And the structure between management system and managed system is shown and process of system information, processor information, backup and restoration of managed PC is illustrated. On real environmental, by monitoring window version, CPU type, system memory and virtual memory and performing backup and restoration of managed PC, actual operation is tested. Management system gathers system information and processor information from managed system and performs backup and restoration for recovering fault of managed system. Hence PC managers can operate and manage many PCs on LAN, efficiently.

• Journal of Internet Computing and Services
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• v.8 no.4
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• pp.51-59
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• 2007

This paper presents the development of RFID educational system based on using 900MHz air interface between the reader and the active tag. The software of reader and the active tag is developed on embedded environment, and the software of PC controlling the reader is based on window OS operated as the server. The AT89C51ED2 VLSI chip is used for the processor of the reader and the active tag. As the development environment, Keil compiler is used for the reader and the active tag of which the programing language is C. The visual C language of the visual studio on the PC activated as the server is used for development language. To verify the function of the system, PC gets the tag's identification number through the reader and send the data to with the active tag memory a certain contents as "wite" operation. Finally the data written from the active tag's memory is sent to the PC via the reader as "read" operation and compare the received data with one already sent to the tag.

• Journal of IKEEE
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• v.24 no.1
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• pp.200-207
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• 2020

In this paper, an area-efficient feature extractor was proposed for security surveillance radar systems and FPGA-based implementation results were presented. In order to reduce the memory requirements, features extracted from Doppler profile for FFT window-size are used, while those extracted from total spectrogram for frame-size are excluded. The proposed feature extractor was design using Verilog-HDL and implemented with Xilinx Zynq-7000 FPGA device. Implementation results show that the proposed design can reduce the logic slice and memory requirements by 58.3% and 98.3%, respectively, compared with the existing research. In addition, security surveillance radar system with the proposed feature extractor was implemented and experiments to classify car, bicycle, human and kickboard were performed. It is confirmed from these experiments that the accuracy of classification is 93.4%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.1-10
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• 2003

Device characteristics of the Metal-Ferroclecric-Semiconductor FET(MFSFET) are simulated in this study. The field-dependent polarization model and the square-law FET model are employed in our simulation. C-V$_{G}$ curves generated from our MFSFET simulation exhibit the accumulation, the depletion and the inversion regions clearly. The capacitance, the subthreshold and the drain current characteristics as a function of gate bias exhibit the memory windows are 1 and 2 V, when the coercive voltages of ferroelectric are 0.5 and 1 V respectively. I$_{D}$-V$_{D}$ curves are composed of the triode and the saturation regions. The difference of saturation drain currents of the MFSFET device at the dual threshold voltages in I$_{D}$-V$_{D}$ curve is 1.5, 2.7, 4.0, and 5.7 ㎃, when the gate biases are 0, 0.1, 0.2 and 0.3V respectively. As the drain current is demonstrated after time delay, PLZT(10/30/70) thin film shows excellent reliability as well as the decrease of saturation current is about 18 % after 10 years. Our simulation model is expected to be very useful in the estimation of the behaviour of MFSFET devices.T devices.

• Journal of KIISE:Software and Applications
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• v.29 no.9
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• pp.654-668
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• 2002

In this paper, we present an empirical study for improving the Korean text chunking based on machine learning and feature set selection approaches. We focus on two issues: the problem of selecting feature set for Korean chunking, and the problem of alleviating the data sparseness. To select a proper feature set, we use a heuristic method of searching through the space of feature sets using the estimated performance from a machine learning algorithm as a measure of "incremental usefulness" of a particular feature set. Besides, for smoothing the data sparseness, we suggest a method of using a general part-of-speech tag set and selective lexical information under the consideration of Korean language characteristics. Experimental results showed that chunk tags and lexical information within a given context window are important features and spacing unit information is less important than others, which are independent on the machine teaming techniques. Furthermore, using the selective lexical information gives not only a smoothing effect but also the reduction of the feature space than using all of lexical information. Korean text chunking based on the memory-based learning and the decision tree learning with the selected feature space showed the performance of precision/recall of 90.99%/92.52%, and 93.39%/93.41% respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.05a
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• pp.91-96
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• 1992

The nonvolatile SNOSFET EEPROM memory devices with the channel width and iength of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] were fabricated by using the actual CMOS 1 [Mbit] process technology. The charateristics of I$\_$D/-V$\_$D/, I$\_$D/-V$\_$G/ were investigated and compared with the channel width and length. From the result of measuring the I$\_$D/-V$\_$D/ charges into the nitride layer by applying the gate voltage, these devices ere found to have a low conductance state with little drain current and a high conductance state with much drain current. It was shown that the devices of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$] represented the long channel characteristics and the devices of 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$] and 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$] represented the short channel characteristics. In the characteristics of I$\_$D/-V$\_$D/, the critical threshold voltages of the devices were V$\_$w/ = +34[V] at t$\_$w/ = 50[sec] in the low conductance state, and the memory window sizes wee 6.3[V], 7.4[V] and 3.4[V] at the channel width and length of 15[$\mu\textrm{m}$]${\times}$15[$\mu\textrm{m}$], 15[$\mu\textrm{m}$]${\times}$1.5[$\mu\textrm{m}$], 1.9[$\mu\textrm{m}$]${\times}$1.7[$\mu\textrm{m}$], respectively. The positive logic conductive characteristics are suitable to the logic circuit designing.