• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.4
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• pp.17-22
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• 2012

Convolution filtering methods have been widely applied to various digital signal processing fields for image blurring, sharpening, edge detection, and noise reduction, etc. According to their application purpose, the filter mask size or shape and the mask value are selected in advance, and the designed filter is applied to input image for the convolution processing. In this paper, we proposed an image processing acceleration method for the convolution processing by using two-dimensional Look-up table (LUT) and overlap-region buffering technique. First, based on the fixed convolution mask value, the multiplication operation between 8 or 10 bit pixel values of the input image and the filter mask values is performed a priori, and the results memorized in LUT are referred during the convolution process. Second, based on symmetric structural characteristics of the convolution filters, inherent duplicated operation region is analysed, and the saved operation results in one step before in the predefined memory buffer is recalled and reused in current operation step. Through this buffering, unnecessary repeated filter operation on the same regions is minimized in sequential manner. As the proposed algorithms minimize the computational amount needed for the convolution operation, they work well under the operation environments utilizing embedded systems with limited computational resources or the environments of utilizing general personnel computers. A series of experiments under various situations verifies the effectiveness and usefulness of the proposed methods.

• The Journal of the Convergence on Culture Technology
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• v.6 no.4
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• pp.813-818
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• 2020

Recently, with the rapid increase in technology and users of smart devices, the smart watch market has grown, and its utility and usability are continuously expanding. The strengths of smartwatches are wearable portability, application immediacy, data diversity and real-time capability. Despite these strengths, smartwatches have limitations such as battery limitations, display and user interface size limitations, and memory limitations. In addition, there is a need to supplement developers and standard devices, operating system standard models, and killer application modules. In particular, monitoring and application of user's biometric information is becoming a major service for smart watches. The biometric information of such a smart watch generates a large amount of data in real time. In order to advance the biometric information service, stable peer-to-peer transmission of sensing data to a remote smartphone or local server storage must be performed. We propose a synchronization method to ensure wireless remote peer-to-peer transmission stability in a smart watch system. We design a wireless peer-to-peer transmission process based on this synchronization method, analyze asynchronous transmission process and proposed synchronous transmission process, and propose a transmission efficiency method according to an increase in transmission amount.

• Journal of KIISE:Information Networking
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• v.30 no.1
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• pp.75-81
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• 2003

User authentication, including confidentiality, integrity over untrusted networks, is an important part of security for systems that allow remote access. Using human-memorable Password for remote user authentication is not easy due to the low entropy of the password, which constrained by the memory of the user. This paper presents a new password authentication and key agreement protocol suitable for authenticating users and exchanging keys over an insecure channel. The new protocol resists the dictionary attack and offers perfect forward secrecy, which means that revealing the password to an attacher does not help him obtain the session keys of past sessions against future compromises. Additionally user passwords are stored in a form that is not plaintext-equivalent to the password itself, so an attacker who captures the password database cannot use it directly to compromise security and gain immediate access to the server. It does not have to resort to a PKI or trusted third party such as a key server or arbitrator So no keys and certificates stored on the users computer. Further desirable properties are to minimize setup time by keeping the number of flows and the computation time. This is very useful in application which secure password authentication is required such as home banking through web, SSL, SET, IPSEC, telnet, ftp, and user mobile situation.

• KIPS Transactions on Computer and Communication Systems
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• v.1 no.2
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• pp.71-78
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• 2012

The digital tachograph is a device that automatically records speed and distance of a vehicle, together with the driver's activity and vehicle status at an accident. It records vehicle speed, break status, acceleration, engine RPM, longitude and latitude of GPS, accumulated distance, and so on. European Commission regulation made digital tachographs mandatory for all trucks from 2005. Republic of Korea made digital tachographs mandatory for all new business vehicles from 2011 and is widening the range of vehicles that must install digital tachographs year by year. This device is used to analyze driver's daily driving information and car accidents. Under a car accident that makes the device reliability unpredictable, it is very important to store driving information with maximum reliability for its original mission. We designed and implemented a practical digital tachograph. This paper presents a storage scheme that consists of a first storage device with small capacity at a high reliability and a second storage device with large capacity at a low cost in order to reliably records data with a hardware at a low cost. The first storage device records data in a SLC NAND flash memory in a log-structured style. We present a reverse partial scan that overcomes the slow scan time of log-structured storages at the boot stage. The scheme reduced the scan time of the first storage device by 1/50. In addition, our design includes a scheme that fast stores data at a moment of accident by 1/20 of data transfer time of a normal method.

• The KIPS Transactions:PartA
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• v.19A no.3
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• pp.129-138
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• 2012

In distributed memory architectures like clusters, each node stores a portion of data. How data is distributed across nodes influences the performance of such systems. The data distribution scheme is the strategy to distribute data across nodes and realize parallel data processing. Due to various reasons such as maintenance, scale up, upgrade, etc., the performance of nodes in a cluster can often become non-identical. In such clusters, data distribution without considering performance cannot efficiently distribute data on nodes. In this paper, we propose a new data distribution scheme based on the number of cores in nodes. We use the number of cores as the performance factor. In our data distribution scheme, each node is allocated an amount of data proportional to the number of cores in it. We implement our data distribution scheme using the Chapel language. To show our data distribution is effective in reducing the execution time of parallel applications, we implement Mandelbrot Set and ${\pi}$-Calculation programs with our data distribution scheme, and compare the execution times on a cluster. Based on experimental results on clusters of 8-core and 16-core nodes, we demonstrate that data distribution based on the number of cores can contribute to a reduction in the execution times of parallel programs on clusters.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.35-41
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• 2020

Fast Fourier transform (FFT) processors have been widely used in various application such as communications, image, and biomedical signal processing. Especially, high-performance and low-power FFT processing is indispensable in OFDM-based communication systems. This paper presents a novel radix-26 FFT algorithm with low computational complexity and high hardware efficiency. Applying a 7-dimensional index mapping, the twiddle factor is decomposed and then radix-26 FFT algorithm is derived. The proposed algorithm has a simple twiddle factor sequence and a small number of complex multiplications, which can reduce the memory size for storing the twiddle factor. When the coefficient of twiddle factor is small, complex constant multipliers can be used efficiently instead of complex multipliers. Complex constant multipliers can be designed more efficiently using canonic signed digit (CSD) and common subexpression elimination (CSE) algorithm. An efficient complex constant multiplier design method for the twiddle factor multiplication used in the proposed radix-26 algorithm is proposed applying CSD and CSE algorithm. To evaluate performance of the previous and the proposed methods, 256-point single-path delay feedback (SDF) FFT is designed and synthesized into FPGA. The proposed algorithm uses about 10% less hardware than the previous algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.896-905
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• 2010

The sensor networks can be used attractively for various application areas. Time synchronization is important for any Ubiquitous Sensor Networks (USN) systems. USN makes extensive use of synchronized time in many contexts for data fusion. However existing time synchronization protocols are available only for homogeneous sensor nodes of USN. It needs to be extended or redesigned in order to apply to the USN with heterogeneous sensor nodes. Because heterogeneous sensor nodes have different clock sources with the SinkNode of USN, it is impossible to be synchronized global time. In addition, energy efficiency is one of the most significant factors to influence the design of sensor networks, as sensor nodes are limited in power, computational capacity, and memory. In this paper, we propose specific time synchronization based on master-slave topology for the global time synchronization of USN with heterogeneous sensor nodes. The time synchronization master nodes are always able to be synchronized with the SinkNode. Then time synchronization master nodes enable time synchronization slave nodes to be synchronized sleep periods. The proposed master-slave time synchronization for heterogeneous sensor nodes of USN is also helpful for power saving by maintaining maximum sleep time.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.69-78
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• 2009

One of the most effective way to improve cache performance is to exploit both temporal and spatial locality given by any program executive characteristics. In this paper we present a high performance and low power cache structure with a bank selection mechanism that enhances exploitation of spatial and temporal locality. The proposed cache system consists of two parts, i.e., a main direct-mapped cache with a small block size and a fully associative buffer with a large block size as a multiple of the small block size. Especially, the main direct-mapped cache is constructed as two banks for low power consumption and stores a small block which is selected from fully associative buffer by the proposed bank selection algorithm. By using the bank selection algorithm and three state bits, We selectively extend the lifetime of those small blocks with high temporal locality by storing them in the main direct-mapped caches. This approach effectively reduces conflict misses and cache pollution at the same time. According to the simulation results, the average miss ratio, compared with the Victim and STAS caches with the same size, is improved by about 23% and 32% for Mibench applications respectively. The average memory access time is reduced by about 14% and 18% compared with the he victim and STAS caches respectively. It is also shown that energy consumption of the proposed cache is around 10% lower than other cache systems that we examine.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.739-752
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• 2002

Recently, to utilize the limited bandwidth effectively, the concept of partial response (PR) signaling has widely been adopted in both the high-speed data transmission and high-density digital recording/playback systems such as digital microwave, digital subscriber loops, hard disk drives, digital VCR's and digital versatile recordable disks and so on. This paper is concerned with adaptive equalization of partial response channels particularly for the magnetic recording channels. Specifically we study how the PR channel equalizers work for different choices of desired or reference signals used for adjusting the equalizer weights. In doing so, we consider three different configurations that are actually implemented in the commercial products mentioned above. First of all, we show how to compute the theoretical values of the optimum Wiener solutions derived by minimizing the mean-squared error (MSE) at the equalizer output. Noting that this equalizer MSE measure cannot be used to fairly compare the three configurations, we propose to use the data MSE that is computer just before the final detector for the underlying PR system. We also express the data MSE in terms of the channel impulse response values, source data power and additive noise power, thereby making it possible to compare the performance of the configurations under study. The results of extensive computer simulation indicate that our theoretical derivation is correct with high precision. Comparing the three configurations, it also turns out that one of the three configurations needs to be further improved in performance although it has an apparent advantage over the others in terms of memory size when implemented using RAM's for the decision feedback part.