• 대한임베디드공학회논문지
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• 제11권2호
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• 한국통신학회논문지
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• 제37권8A호
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• pp.706-711
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• 2012

멀티레벨셀 낸드 플래시 메모리는 한 셀에 2비트 이상의 데이터를 저장 할 수 있는 기술이다. 현재 2비트를 한 셀에 저장하는 기술만 상용화 되었다. 이는 3비트 이상을 저장하게 되면, 각 레벨의 간격이 좁아져서 데이터의 오류가 많이 발생하는데 이를 극복하기가 어렵다. 오류의 원인으로 여러 가지가 있지만, 그 중에서도 커플링 잡음이 가장 문제가 된다. 따라서 본 논문에서는 4비트를 한 셀에 저장하는 채널에 커플링 잡음을 가정하여 성능의 개선을 실험하였으며, 메모리 공간을 줄이기 위하여 커플링 제거기에 윈도우 크기의 데이터를 활용하여 성능을 비교하였다. 플래시 메모리에서 데이터를 읽는 가장 기본 방법인 문턱 전압 비교 방법을 구현하여 제안한 방법과 성능을 비교 하였다.

• 동의생리병리학회지
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• 제17권2호
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• pp.553-559
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• 2003

In order to make the efficient prescription and cope with various senile dementia, learning and memory functions of Sprague-Dawley model rats were tested with Morris water maze at first. And to evaluate the effects of the sample drug(GM) on choline acetyltranferase and acetylcholine esterase, immunoreactive measurement and enzymatic activity measuring were carried out. Rats were injected with ibotenic acid through hippocampus CA1 and CA3 area. The results are as following. GM improves the learning ability in tile acquisition test and memory function in the retention test significantly. And GM increases the level of ChAT which is synthesizing acetylcholine in CA3 area, and at the same time it increases the level of AChE which is resolving acetylcholine. These results show that GM improve the cholinergic catabolism and anabolism, and the increment of metabolic activity of cholinergic system contributes to the recovery of damaged learning and memory function by ibotenic acid. So it can be concluded that GM will be helpful to cholinergic brain disease induced by primary or senile reduction of acetylcholine secretive activity.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• 한국정보과학회논문지:시스템및이론
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• 제30권7_8호
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• pp.331-340
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• 2003

가격대비 성능이 좋은 저가의 상업용 SMP가 클러스터 시스템의 노드로 많이 사용되고 있다. 본 논문에서는 이러한 SMP 클러스터 상에서 KDSM을 확장해 소프트웨어 분산공유메모리를 구현하고 성능을 평가하였다. 본 논문의 SDSM 시스템은 HLRC 메모리 모델을 제공한다. 또한 같은 SMP 노드내에서 실행되는 프로세스 간에는 메모리 공유를 통해 페이지 획득 및 메시지 전달을 줄여 성능을 향상시켰다. 100Mbps Fast Ethernet으로 연결된 8노드의 2-way 펜티엄-III SMP 클러스터 상에서 구현되었고 통신계층은 TCP/IP를 사용한다. 8개의 응용프로그램을 실행시켜 얻은 성능 평가에서는 기존의 단일프로세스 프로토콜과 비교해 최대 33%의 성능 향상과 13%-52%의 페이지 획득 감소가 나타났다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.154-155
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• 2007

PRAM(Phase-Change RAM) is a promising memory that can solve the problem of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. So, we studied new constitution of $Ge_1Se_1Te_2$ chalcogenide material and presented the method of reducing the contact size between $Ge_1Se_1Te_2$ and electrode. A small-contact-area electrode is used primarily to supply current into and minimize heat loss from the chalcogenide. In this letter, we expect the method of reducing the contact size between $Ge_1Se_1Te_2$ and electrode to decrease writing current.

• 한국정보과학회논문지:시스템및이론
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• 제28권9호
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• pp.461-468
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• 2001

공유가상메모리 시스템은 적은 비용으로 고성능 계산 능력을 제공하지만, 메모리 접근 지연 시간이 길다는 문제점이 있다. 일반적으로 이 지연시간은 공유데이터에 대한 반복적인 무효화 작업에 의해 일어난다. 고유 데이터들은 동기화를 통해서 접근되고 쓰레드를 반복적 패턴에 의해 동기화 되기 때문에, 반복성에 기반한 선인출 기법은 메모리 지연시간을 효과적으로 줄일수 있다. 본 논문에서는 동기화 변수별로 접근 기록을 분석해서 미래의 메모리 접근을 예측하는 선인출 기법을 제안한다. 제안하는 기법은 8노드 클러스터상에서 SPLASH-2 응용들을 실행시켜 성능을 측정하였다. 그 결과, 제안하는 기법이 34%~45%정도의 메모리 접근 지연시간을 감소할수 있었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.108-109
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• 2012

This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

• 생약학회지
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• 제46권3호
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• pp.243-249
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• 2015

Myrrh, Angelicae Radix, and Schisandrae Fructus have been used to treat diverse diseases including neurological disorder in the traditional Korean medicine. In the present study, we investigated the ameliorating effects of HPM-1, a combined extract of Myrrh, Angelicae Radix and Schisandrae Fructus, on scopolamine-induced memory impairments in mice. First, we assessed HPM-1, HPM-2 and HPM-3, in which Myrrh was extracted with water, 30% ethanol, and 30% ethanol/3% vinegar, respectively. The oral administration of HPM-1, HPM-2, or HPM-3 significantly reversed scopolamine-induced reduction of spontaneous alternation in the Y-maze task. In the passive avoidance task, HPM-1 or HPM-3 restored the decreased latency time of the retention trial by scopolamine treatment, but in terms of efficacy, HPM-1 showed more beneficial effects than HPM-3. In addition, HPM-1 administration reversed scopolamine-induced reduction of spontaneous alternation in the Y-maze task and scopolamine-decreased latency time in the passive avoidance in a dose-dependent manner. These results suggest that HPM-1 has the therapeutic potential in memory impairments.

• 한국멀티미디어학회논문지
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• 제14권7호
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• pp.917-923
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• 2011

본 논문에서는 JPEG2000 부호화 시스템의 과도한 메모리 요구 사항을 감소시키기 위해 예측 부호화 기반의 새로운 임베디드 압축(Embedded Compression, EC) 알고리즘을 제안한다. 본 논문의 EC 기법은 EC가 적용되지 않은 DWT 프로세서와 비교하여 DWT 과정에서 발생하는 임시적인 저주파 웨이블릿 계수들의 메모리 접근 및 크기를 50 %로 줄일 수 있다. 무손실의 영상 압축 시스템에 널리 쓰이면서 단순하지만 좋은 성능을 갖는 LOCO-I(LOw COmplexity LOssless COmpression for Image)와 MAP(Median Adaptive Predictor) 예측기를 제안한 EC 알고리즘에 적용하였다. 제안한 예측 기반의 EC 알고리즘은 예측 오차 값들을 인코딩하기 위하여 포워드 적응형 양자화와 고정 길이 코드를 사용한다. 시뮬레이션 결과를 통해 예측기가 LOCO-I와 MAP인 경우, 본 논문에서 제안한 EC 알고리즘에 의한 평균적인 PSNR 저하는 각각 0.48 dB와 0.26 dB임을 알 수 있다. 선행 논문 [9]에서 제안한 하다마드 변환(MHT) 기반의 EC 알고리즘과 비교하여 평균적인 PSNR이 약 1.39 dB 향상된다.