• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.947-960
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• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• Journal of Advanced Navigation Technology
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• v.19 no.5
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• pp.423-432
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• 2015

This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.

• Journal of Korea Spatial Information System Society
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• v.9 no.2
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• pp.13-23
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• 2007

Recently there is growing Interest in LBS(Location Based Service) requiring real-time services and the spatial main memory DBMS for efficient Telematics services. In order to optimize existing disk-based multi-dimensional Indexes of the spatial main memory DBMS in the main memory, multi-dimensional index structures have been proposed, which minimize failures in cache access by reducing the entry size. However, because the reduction of entry size requires compression based on the MBR of the parent node or the removal of redundant MBR, the cost of MBR reconstruction increases in index update and the efficiency of search is lowered in index search. Thus, to reduce the cost of MBR reconstruction, this paper proposed the RSMBR(Relative-Sized MBR) compression technique, which applies the base point of compression differently in case of broad distribution and narrow distribution. In case of broad distribution, compression is made based on the left-bottom point of the extended MBR of the parent node, and in case of narrow distribution, the whole MBR is divided into cells of the same size and compression is made based on the left-bottom point of each cell. In addition, MBR was compressed using a relative coordinate and size to reduce the cost of search in index search. Lastly, we evaluated the performance of the proposed RSMBR compression technique using real data, and proved its superiority.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.41-50
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• 2009

The flash memory has many advantages such as low power consumption, strong shock resistance, fast I/O and non-volatility. And it is increasingly used in the mobile storage device. Many researchers are studying the YAFFS, NAND flash file system, which is widely used in the embedded device. However, the existing YAFFS has two problems. First, it takes long time to mount the YAFFS file system because it scans whole spare areas in all pages. Second, the cleaning policy of the YAFFS does not consider the wear-leveling so that it cannot guarantee the duration of data completely. In order to solve these problems, this paper proposes a new content-based YAFFS that consists of a mounting time reduction technique and a content-cleaning policy by using content-based block management. The proposed method only scans partial spare areas of some special pages and provides the block swapping which enables the wear-leveling of data blocks. We performed experiments to compare the performance of the proposed method with those of the JFFS2 system and YAFFS system. Experimental results show that the proposed method reduces the average mounting time by 82.2% comparing with JFFS2 and 42.9% comparing with YAFFS. Besides, it increases the life time of the flash memory by 35% comparing with the existing YAFFS whereas no overheat is added.

• Korean Journal of Materials Research
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• v.9 no.3
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• pp.322-326
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• 1999

In this study, cold-rolling and appropriate annealing was adopted for the grain refining of Cu-26.65Zn-4. 05Al-0.31Ti(wt%) shape memory alloy. For the cold deformation of this alloy the ducti1e $\alpha$-phase must be contained. After heat treatment at $550^{\circ}C$ the $(\alpha+$\beta)$-dual phase with 40vol.% $\alpha$-phase was obtained which could be rolled at room temperature. This alloy was cold rolled into a final thickness of 1.0mm with total reduction degrees of 70% and 90%. The rolled sheets were betanized at $800^{\circ}C$ for various times, then quenched into ice water. The grain size of co]d rolled samples were $60~80\mu\textrm{m}$ which is much smaller comparing with the hot-rolled samples. And the 90% rolled sample showed smaller grain size than the case of the 70% rolled one. The small grain size had influence on the phase transformation temperatures and stabilization of the austenitic phases.

• Journal of Advanced Navigation Technology
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• v.11 no.3
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• pp.239-251
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• 2007

This thesis is about the reduction of the power consumption in GPS embedded terminals with periodic position fix to improve the time delay of position determination. In order to improve time delay of position determination during the wireless terminal is powered on, it needs to be set such that it can be periodically recalibrated by the GPS and those recalibrated values need to be saved in the terminal's memory so that it can reduce the time delay from the request of location. By using the trace of the information that's been saved in the terminal's memory, it can be set so that it'll be easier to determine whether the wireless terminal has gone into buildings and have the capability of checking if it has gone into a specific building. Likewise, while the terminal is turned on, in order calibrate the location, it needs to continuously work the GPS engine which leads to a rapid decrease in terminal's idle time. This thesis proposes some solutions regarding these issues - reducing 20 ~ 30% of the battery consumption for GPS visible situation that can occur when the wireless terminal periodically calibrates its location to determine the in-building status, and extending the idle time of the terminal by flexibly using the suggested GPS calibration time method according to wireless terminal's mobility.

• Journal of Information Technology Services
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• v.12 no.4
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• pp.369-380
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• 2013

The advent of the state-of-the-art technologies such as cloud computing and big data processing stimulates the provision of various new IT services, which implies that more servers are required to support them. However, the need for more servers will lead to more energy consumption and the efficient use of energy in the computing environment will become more important. The next generation nonvolatile RAM has many desirable features such as byte addressability, low access latency, high density and low energy consumption. There are many approaches to adopt them especially in the area of the file system involving storage devices, but their focus lies on the improvement of system performance, not on energy reduction. This paper suggests a novel approach for energy reduction in which the MRAM-based SSD is utilized as a storage device instead of the hard disk and a downsized page is adopted instead of the 4KB page that is the size of a page in the ordinary file system. The simulation results show that energy efficiency of a new approach is very effective in case of accessing the small number of bytes and is improved up to 128 times better than that of NAND Flash memory.

• Journal of Korea Multimedia Society
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• v.6 no.7
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• pp.1169-1177
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• 2003

The blocking effect results from independent coding of each image block and becomes highly visible, especially coded at very low bit rates. In this paper, a blocking effect reduction circuit is designed which is composed of a memory, arithmetic and logic unit, and control block. The circuit is based on a rational open uniform B-spline curve that uses to produce a smooth curve through a set of control points. The weight values and the modified pixel values in a rational open uniform B-spline curve are calculated using arithmetic and logic circuits. The simulation results show that the circuit has excellent performance for ail pattern of the blocking effects.

• Journal of Oriental Neuropsychiatry
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• v.24 no.3
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• pp.245-250
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• 2013

Objectives : Psychasthenia is a psychological disorder that is characterized by phobias, obsessions, compulsions, or excessive anxiety. Their thoughts can be scattered and require significant effort to organize, often resulting in sentences that do not come out as intended, making little sense to others. Methods : Two Patients with psychasthenia are unable to resist specific actions or thoughts, regardless of their maladaptive nature and have insufficient control over their conscious thinking and memory, sometimes wandering aimlessly and/or forgetting what they were doing. Results : The constant mental effort induces physiological fatigue, which worsens the condition. Nevertheless, psychasthenia has become a forgotten disorder. We observed two cases that are worthy of the original definition of psychasthenia. Conclusions : It can be concluded that patients with psychasthenia complain of sinking because of a reduction in psychological tension or an effort to recover the reduction in tension.

• Structural Engineering and Mechanics
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• v.38 no.4
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• pp.429-441
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• 2011

In large-scale problem, a huge size of computational resources is needed for a reliable solution which represents the detailed description of dynamic behavior. Recently, eigenvalue reduction schemes have been considered as important technique to resolve computational resource problems. In addition, the efforts to advance an efficiency of reduction scheme leads to the development of the multi-level system condensation (MLSC) which is initially based on the two-level condensation scheme (TLCS). This scheme was proposed for approximating the lower eigenmodes which represent the global behavior of the structures through the element-level energy estimation. The MLSC combines the multi-level sub-structuring scheme with the previous TLCS for enhancement of efficiency which is related to computer memory and computing time. The present study focuses on the implementation of the MLSC on the direct time response analysis and the frequency response analysis of structural dynamic problems. For the transient time response analysis, the MLSC is combined with the Newmark's time integration scheme. Numerical examples demonstrate the efficiency of the proposed method.