• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.410-410
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• 2013

Next-generation nonvolatile memory (NVM) has attracted increasing attention about emerging NVMs such as ferroelectric random access memory, phase-change random access memory, magnetic random access memory and resistance random access memory (RRAM). Previous studies have demonstrated that RRAM is promising because of its excellent properties, including simple structure, high speed and high density integration. Many research groups have reported a lot of metal oxides as resistive materials like TiO2, NiO, SrTiO3 and ZnO [1]. Among them, the ZnO-based film is one of the most promising materials for RRAM because of its good switching characteristics, reliability and high transparency [2]. However, in many studies about ZnO-based RRAMs, there was a problem to get lower current level for reducing the operating power dissipation and improving the device reliability such an endurance and an retention time of memory devices. Thus in this paper, we investigated that highly reproducible bipolar resistive switching characteristics of W doped ZnO RRAM device and it showed low resistive switching current level and large ON/OFF ratio. This may be caused by the interdiffusion of the W atoms in the ZnO film, whch serves as dopants, and leakage current would rise resulting in the lowering of current level [3]. In this work, a ZnO film and W doped ZnO film were fabricated on a Si substrate using RF magnetron sputtering from ZnO and W targets at room temperature with Ar gas ambient, and compared their current levels. Compared with the conventional ZnO-based RRAM, the W doped ZnO ReRAM device shows the reduction of reset current from ~$10^{-6}$ A to ~$10^{-9}$ A and large ON/OFF ratio of ~$10^3$ along with self-rectifying characteristic as shown in Fig. 1. In addition, we observed good endurance of $10^3$ times and retention time of $10^4$ s in the W doped ZnO ReRAM device. With this advantageous characteristics, W doped ZnO thin film device is a promising candidates for CMOS compatible and high-density RRAM devices.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.699-708
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• 2006

Bus splitting technique reduces bus energy by placing modules with frequent communications closely and using necessary bus segments in communications. But, previous bus splitting techniques can not be used in MPSoC platform, because it uses cache coherency protocol and all processors should be able to see the bus transactions. In this paper, we propose a bus splitting technique for MPSoC platform to reduce bus energy. The proposed technique divides a bus into several bus segments, some for private memory and others for shared memory. So, it minimizes the bus energy consumed in private memory accesses without producing cache coherency problem. We also propose a task allocation technique considering cache coherency protocol. It allocates tasks into processors according to the numbers of bus transactions and cache coherence protocol, and reduces the bus energy consumption during shared memory references. The experimental results from simulations say the bus splitting technique reduces maximal 83% of the bus energy consumption by private memory accesses. Also they show the task allocation technique reduces maximal 30% of bus energy consumed in shared memory references. We can expect the bus splitting technique and the task allocation technique can be used in multiprocessor platforms to reduce bus energy without interference with cache coherency protocol.

• Korean Journal of Acupuncture
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• v.19 no.2
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• pp.63-78
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• 2002

Kupunggibodan(KU), Gamisamul-tang(GA) and Whangryunhaedok-tang(WH) are clinically the most popular prescriptions as an herbal medicine in the treatment of ischemia. In order to compare and evaluate their protective effects on the ischema-induced cognitive deficits by middle cerebral artery occlusion (MCAO), we examined its ability to improve ischemia-induced cell loss and impairements of learning and memory in the Morris water maze and eight-arm radial arm maze. Focal cerebral ischemia produced a marked cell loss, decrease in acetylcholinesterase(AchE) reactivity in the hippocampus, and learning and memory deficits in two behavioral tasks. Pretreatment with WH (100 mg/kg, p.o.) produced a substantial increase in acquisition in the Morris water maze. Pretreatment with KU increased the perfomance of the resention test in the Morris water maze. WH, KU and GA caused a significant improvement in choice accuracy in radial arm maze test. WH was superior to KU and GA in perfomance of the radial arm maze test. Consistent with behavioral data, staining with cresyl violet showed that pretreatments with WH, but not KU and GA significantly recovered the ischemia-induced cell loss in the hippcampal CA1 area. In addition, pretreatments with WH and KU recovered the ischemia-induced reduction of AchE reactivity in the hippocampal CA1 area. These results demonstrated that KU, GA and WH have protective effects against ischimea-induced learning and memory impairments and that the efficacy was the order of WH>KU>GA in tratment of ischemia induced memory deficits. The present studies provide an evidence of KU, GA and WH as putative treatment of vascular dementia. Supported by a fund from the Ministry of Health and Welfare(HMP-00-OO-04-0004), and the Brain Korea 21 Project from Korean Ministry of Education, Korea.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.5
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• pp.88-94
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• 2009

We propose a scheme which reduce the computational complexity of the lattice reduction (LR) aided detector in MIMO system. The performance of the ML detection algorithm is good but the computational complexity grows exponentially with the number of antenna elements and constellation points. LR aided detector shows the same diversity with the ML scheme with relatively less complexity. But the LR scheme still requires many computations since it involves several iterations of size reduction and column vector exchange. We notice that the LR process depends not on the received signal but only on the channel matrix so we can apply LR process offline and store the results in Look-Up Table (LUT). In this paper we propose an algorithm to generate the LUT which require less memory requirement and we evaluate the performance and complexity of the proposed system. We show that the proposed system requires less computational complexity with similar detection performance compared with the conventional LR aided detector.

• Smart Structures and Systems
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• v.31 no.1
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• pp.89-100
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• 2023

This paper conducts a parametric study of a new tuned mass damper with pre-strained superelastic SMA helical springs (SMAS-TMD) on the vibration reduction effect. First, a force-displacement relation model of superelastic SMA helical spring is presented based on the multilinear constitutive model of SMA material, and the tension tests of the six SMA springs fabricated are implemented to validate the mechanical model. Then, a dynamic model of a single floor steel frame with the SMAS-TMD damper is set up to simulate the seismic responses of the frame, which are testified by the shaking table tests. The wire diameter, initial coil diameter, number of coils and pre-strain length of SMA springs are extracted to investigate their influences on the seismic response reduction of the frame. The numerical and experimental results show that, under different earthquakes, when the wire diameter, initial coil diameter and number of coils are set to the appropriate values so that the initial elastic stiffness of the SMA spring is between 0.37 and 0.58 times of classic TMD stiffness, the maximum reduction ratios of the proposed damper can reach 40% as the mass ratio is 2.34%. Meanwhile, when the pre-strain length of SMA spring is in a suitable range, the SMAS-TMD damper can also achieve very good vibration reduction performance. The vibration reduction performance of the SMAS-TMD damper is generally equal to or better than that of the classic optimal TMD, and the proposed damper effectively suppresses the detuning phenomena that often occurs in the classic TMD.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.1
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• pp.25-39
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• 2018

NIST(National Institute of Standards and Technology) has recently published SP 800-90B second draft which is the document for evaluating security of entropy source, a key element of a cryptographic random number generator(RNG), and provided a tool implemented on Python code. In SP 800-90B, the security evaluation of the entropy sources is a process of estimating min-entropy by several estimators. The process of estimating min-entropy is divided into IID track and non-IID track. In IID track, the entropy sources are estimated only from MCV estimator. In non-IID Track, the entropy sources are estimated from 10 estimators including MCV estimator. The running time of the NIST's tool in non-IID track is approximately 20 minutes and the memory usage is over 5.5 GB. For evaluation agencies that have to perform repeatedly evaluations on various samples, and developers or researchers who have to perform experiments in various environments, it may be inconvenient to estimate entropy using the tool and depending on the environment, it may be impossible to execute. In this paper, we propose high-speed implementations and an efficient memory usage technique for min-entropy estimation algorithm of SP 800-90B. Our major achievements are the three improved speed and efficient memory usage reduction methods which are the method applying advantages of C++ code for improving speed of MultiMCW estimator, the method effectively reducing the memory and improving speed of MultiMMC by rebuilding the data storage structure, and the method improving the speed of LZ78Y by rebuilding the data structure. The tool applied our proposed methods is 14 times faster and saves 13 times more memory usage than NIST's tool.

• Journal of IKEEE
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• v.16 no.3
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• pp.265-273
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• 2012

Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

• Wind and Structures
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• v.9 no.3
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• pp.231-243
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• 2006

An improvement to the spectral representation algorithm for the simulation of wind velocity fields on large scale structures is proposed in this paper. The method proposed by Deodatis (1996) serves as the basis of the improved algorithm. Firstly, an interpolation approximation is introduced to simplify the computation of the lower triangular matrix with the Cholesky decomposition of the cross-spectral density (CSD) matrix, since each element of the triangular matrix varies continuously with the wind spectra frequency. Fast Fourier Transform (FFT) technique is used to further enhance the efficiency of computation. Secondly, as an alternative spectral representation, the vectors of the triangular matrix in the Deodatis formula are replaced using an appropriate number of eigenvectors with the spectral decomposition of the CSD matrix. Lastly, a turbulent wind velocity field through a vertical plane on a long-span bridge (span-wise) is simulated to illustrate the proposed schemes. It is noted that the proposed schemes require less computer memory and are more efficiently simulated than that obtained using the existing traditional method. Furthermore, the reliability of the interpolation approximation in the simulation of wind velocity field is confirmed.

• Journal of Korean Institute of Industrial Engineers
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• v.36 no.3
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• pp.193-202
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• 2010

The recommender system is a typical software solution for personalized services which are now popular in e-commerce sites. Most of the existing recommender systems are based on customers' explicit rating data on items (e.g., ratings on movies), and it is only recently that recommender systems based on implicit ratings have been proposed as a better alternative. Implicit ratings of a customer on those items that are clicked but not purchased can be inferred from the customer's navigational and behavioral patterns. In this article, a dimensionality reduction (DR) technique is newly applied to the implicit rating-based recommender system, and its effectiveness is assessed using an experimental e-commerce site. The experimental results indicate that the performance of the proposed approach is superior or at least similar to the conventional collaborative filtering (CF)-based approach unless the number of recommended products is 'large.' In addition, the proposed approach requires less memory space and is computationally more efficient.