• Journal of Aerospace System Engineering
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• v.18 no.1
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• pp.1-10
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• 2024

In a previous study, a structure of a superplastic yoke consisting of a thin FR4 layer laminated with viscoelastic tape on both sides of a shape memory alloy (SMA) was proposed to reduce residual vibration generated by a deployable solar panel during high motion of a satellite. Damping properties of viscoelastic tapes will change with temperature, which can directly affect vibration reduction performance of the yoke. To check damping performance of the yoke at different temperatures, free damping tests were performed under various temperature conditions to identify the temperature range where the damping performance was maximized. Based on above temperature test results, this paper predicts temperature of the yoke through orbital thermal analysis so that the yoke can have effective damping performance even if it is exposed to an orbital thermal environment. In addition, the thermal design method was described so that the yoke could have optimal vibration reduction performance.

• Steel and Composite Structures
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• v.3 no.6
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• pp.403-420
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• 2003

In the paper one investigates the benefits deriving from the introduction of SMA provisions in a structure subject to dynamic excitation and vertical loads. At this purpose one considers a multi-degree-of-freedom (mdof) shear elastic-plastic frame and designs couples of super-elastic SMA tendons to be placed at critical locations of the structure. Particular attention is focused on the reduction of $P-{\Delta}$ effects.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1933_1934
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• 2009

This research is about the remote control of the infra-ray signal producer and the received signal memory-type control unit. Also by using the infra-ray signal from the remote control, reduction of malfunctions due to infra-ray signal from other devices are presented. Applications on various electric and electronic items to improve the convenience are also shown.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.2
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• pp.344-352
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• 1997

This paper proposes an efficient lossless coding scheme for tree structured vector quantization (TSVQ) system which efficiently exploits inter-block correlation. The TSVQ index of the current block is adaptively arithmeticencoded depending on the indices of the previous blocks. This paper also presents a reductio method, which effectively resolve the memory problem which usually arises in many conditional entropy coding schemes. Simulation results show that the proposed scheme provides remarkable bitrate reduction by effectively exploiting not only linear but also non-linear inter-block correlation.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.686-691
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• 1992

Implicit guidance algorithm can deal with the trajectory error rapidly, but it has to save much data. If, however, the control variable is represented by a specific function form, a few parameters will suffice to define the control variable. In this paper, we study the method of updating the parameters of the control function for the reduction of trajectory errors. The method proposed here does not require much memory for guidance.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1929-1930
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• 2008

This research is about the remote control of the infra-ray signal producer and the received signal memory-type control unit. Also by using the infra-ray signal from the remote control, reduction of malfunctions due to infra-ray signal from other devices are presented. Applications on various electric and electronic items to improve the convenience are also shown.

• ETRI Journal
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• v.32 no.4
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• pp.596-602
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• 2010

This paper proposes a computationally efficient learning-based super-resolution algorithm using k-means clustering. Conventional learning-based super-resolution requires a huge dictionary for reliable performance, which brings about a tremendous memory cost as well as a burdensome matching computation. In order to overcome this problem, the proposed algorithm significantly reduces the size of the trained dictionary by properly clustering similar patches at the learning phase. Experimental results show that the proposed algorithm provides superior visual quality to the conventional algorithms, while needing much less computational complexity.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.04a
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• pp.61-63
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• 2015

본 논문에서는 애플리케이션 실행에 필요한 파일들을 검출하고, 그 파일들을 저 용량의 비 휘발성 메모리에 옮겨 시작 시간을 단축시킨다. 또한 각각의 파일들은 전체가 필요하지 않고 파일 중 일부분만 필요하기 때문에, 필요한 부분만 주 메모리에 선 적재 함으로써 시작 시간을 크게 개선하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.2
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• pp.241-251
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• 2015

In public-key cryptographic system based on finite field arithmetic, it is very important to challenge for implementing high speed operation. In this paper, we focused on 8-bit ATmega128 processor and concentrated on enhancing efficiency of reduction operation which uses irreducible polynomial $f(x)=x^{271}+x^{207}+x^{175}+x^{111}+1$ and $f(x)=x^{193}+x^{145}+x^{129}+x^{113}+1$. We propose optimized reduction algorithms which are designed to reduce repeated memory accesses by calculating final reduced values of Fast reduction. There are 53%, 55% improvement when proposed algorithm is implemented using assembly language, compare to previous Fast reduction algorithm.

• ETRI Journal
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• v.31 no.5
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• pp.510-517
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• 2009

A high throughput parallel decoding method is developed for context-based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical-operation-based parallel decoder for M=8 and a conventional parallel decoder. High-speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.