• Title/Summary/Keyword: Memory improvement

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Efficient DRAM Buffer Access Scheduling Techniques for SSD Storage System (SSD 스토리지 시스템을 위한 효율적인 DRAM 버퍼 액세스 스케줄링 기법)

  • Park, Jun-Su;Hwang, Yong-Joong;Han, Tae-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.7
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    • pp.48-56
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    • 2011
  • Recently, new storage device SSD(Solid State Disk) based on NAND flash memory is gradually replacing HDD(Hard Disk Drive) in mobile device and thus a variety of research efforts are going on to find the cost-effective ways of performance improvement. By increasing the NAND flash channels in order to enhance the bandwidth through parallel processing, DRAM buffer which acts as a buffer cache between host(PC) and NAND flash has become the bottleneck point. To resolve this problem, this paper proposes an efficient low-cost scheme to increase SSD performance by improving DRAM buffer bandwidth through scheduling techniques which utilize DRAM multi-banks. When both host and NAND flash multi-channels request access to DRAM buffer concurrently, the proposed technique checks their destination and then schedules appropriately considering properties of DRAMs. It can reduce overheads of bank active time and row latency significantly and thus optimizes DRAM buffer bandwidth utilization. The result reveals that the proposed technique improves the SSD performance by 47.4% in read and 47.7% in write operation respectively compared to conventional methods with negligible changes and increases in the hardware.

Review on the Three-Dimensional Magnetotelluric Modeling (MT 법의 3차원 모델링 개관)

  • Kim, Hee-Joon;Nam, Myung-Jin;Song, Yoon-Ho;Suh, Jung-Hee
    • Geophysics and Geophysical Exploration
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    • v.7 no.2
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    • pp.148-154
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    • 2004
  • This article reviews the development of three-dimensional (3-D) magnetotelluric (MT) modeling. The 3-D modeling of electromagnetic fields is essential in understanding the physics of MT soundings, and in implementing an inversion method to reconstruct a 3-D resistivity image. Although various numerical schemes have been developed over the last two decades, practical methods have been quite limited. However, the recent rapid improvement in computer speed and memory, as well as the advance in iterative solution algorithms for a large system of equations, makes it possible to model the MT responses of complex 3-D structures, which have been very difficult to simulate before. The use of staggered grids in finite difference method has become popular, conserving a magnetic flux and an electric current and allowing for realistic discontinuous fields. The convergence of numerical solutions has been greatly accelerated by adopting Krylov subspace methods, proper preconditioning techniques, and static divergence corrections. The vector finite-element method using edge elements is also free from the discontinuity problem, and seems a natural choice for modeling complex structures including irregular topography because its flexibility allows one to capture full geometric complexity.

RSP-DS: Real Time Sequential Patterns Analysis in Data Streams (RSP-DS: 데이터 스트림에서의 실시간 순차 패턴 분석)

  • Shin Jae-Jyn;Kim Ho-Seok;Kim Kyoung-Bae;Bae Hae-Young
    • Journal of Korea Multimedia Society
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    • v.9 no.9
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    • pp.1118-1130
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    • 2006
  • Existed pattern analysis algorithms in data streams environment have researched performance improvement and effective memory usage. But when new data streams come, existed pattern analysis algorithms have to analyze patterns again and have to generate pattern tree again. This approach needs many calculations in real situation that needs real time pattern analysis. This paper proposes a method that continuously analyzes patterns of incoming data streams in real time. This method analyzes patterns fast, and thereafter obtains real time patterns by updating previously analyzed patterns. The incoming data streams are divided into several sequences based on time based window. Informations of the sequences are inputted into a hash table. When the number of the sequences are over predefined bound, patterns are analyzed from the hash table. The patterns form a pattern tree, and later created new patterns update the pattern tree. In this way, real time patterns are always maintained in the pattern tree. During pattern analysis, suffixes of both new pattern and existed pattern in the tree can be same. Then a pointer is created from the new pattern to the existed pattern. This method reduce calculation time during duplicated pattern analysis. And old patterns in the tree are deleted easily by FIFO method. The advantage of our algorithm is proved by performance comparison with existed method, MILE, in a condition that pattern is changed continuously. And we look around performance variation by changing several variable in the algorithm.

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A Study on the Post-Evaluation of Landscape Design Competition based on Ground Theory - Case of Gwanggyo Lake Park in Korea - (근거이론을 활용한 조경현상설계의 사후평가 - 광교호수공원을 사례로 -)

  • Hong, Youn-Soon;Park, Jae-Min
    • Journal of the Korean Institute of Landscape Architecture
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    • v.44 no.5
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    • pp.92-102
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    • 2016
  • While there have many completions of large parks recently under development, there has been a dearth of quality assessments. Studies focused on post-evaluation have been made to resolve this, but most of these are biased toward user satisfaction after completion and therefore behaviour analysis has limitations on solving problemsduring the actual design implementation processes. Therefore, this study examined the internal phenomenon and structure of the implementation process of design competition through the ground theory and microscopic independent perspective. As a result, maintaining the identity and differentiation of parks derived from the preserved design competition scheme contributed greatly to completeness and satisfaction. Outcomes were mainly caused by the trust of public officials as the ordering organization, the will of policy decision-makers, and the competence of operational enterprises, etc. Negative factors such as undermining the whole concept of the park and landscape occurred as external pressure and related subjects intruded on change design factors due to variations in social conditions. Additionally, illogical construction processes occurred, such as a reinvestigation of the budget for restoration after damaging on original landscape. There have been needs for the improvement of the work processing system. On balance, an interventional role is very important in the park construction process, especially the PA and operation committee in terms of maintaining the basic direction, landscape design supervision for detailed designs, and expert construction management on LA in terms of rational work management in the field. The study, using the microscopic perspective of the designer and ground theory, deliver significant meaning as an early study by suggesting alternative methods for the after-evaluation of large parks and structurally looking into main influence factors driven during the construction process.

Hardware Design for JBIG2 Encoder on Embedded System (임베디드용 JBIG2 부호화기의 하드웨어 설계)

  • Seo, Seok-Yong;Ko, Hyung-Hwa
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.2C
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    • pp.182-192
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    • 2010
  • This paper proposes the hardware IP design of JBIG2 encoder. In order to facilitate the next generation FAX after the standardization of JBIG2, major modules of JBIG2 encoder are designed and implemented, such as symbol extraction module, Huffman coder, MMR coder, and MQ coder. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the synthesis of VHDL code. To minimize the memory usage, 128 lines of input image are processed succesively instead of total image. The synthesized IPs are downloaded to Virtex-4 FX60 FPGA on ML410 development board. The four synthesized IPs utilize 36.7% of total slice of FPGA. Using Active-HDL tool, the generated IPs were verified showing normal operation. Compared with the software operation using microblaze cpu on ML410 board, the synthesized IPs are better in operation time. The improvement ratio of operation time between the synthesized IP and software is 17 times in case of symbol extraction IP, and 10 times in Huffman coder IP. MMR coder IP shows 6 times faster and MQ coder IP shows 2.2 times faster than software only operation. The synthesized H/W IP and S/W module cooperated to succeed in compressing the CCITT standard document.

An XML based Mobile Information Visualization System for Mobile Devices using Information layout Techniques (Rectangle Layout을 이용한 XML 기반 모바일 정보 시각화 시스템)

  • Yoo Hee-Yong;Cheon Suh-Hyun
    • Journal of KIISE:Software and Applications
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    • v.33 no.9
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    • pp.776-786
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    • 2006
  • This paper proposes XML based mobile information visualization system using rectangle layout to show effectively XML based information to user on mobile devices which do not have a rich display feature. We define XML schema that can describes information in graph with cycle as well as information in tree form. It suggests using rectangle layout method that is an improvement of the traditional method of the radial layout because the specificity of the mobile display should be considered when XML information is rendered on the screen. And then, it applies DOI of fisheye view algorithm to information on the rectangle layout to represent all and user interest information. And it also suggests an effective method considering capability of mobile devices to decrease user's confusion and improve awareness of user when a user Interest target selected. The proposed information visualization system in the form of focus+context supports an effective interface for information retrieval via mobile devices, such as PDA, cellular phone and smart phone, that usually have less power of CPU than that of PC and the constraints of display and memory. In this paper, it performs experiments and makes an evaluation comparing information visualization method between the traditional radial layout and the proposed rectangle layout.

Study on White Ginseng Extract Preparation for Cognition Improvement (인지능 개선 효과 증진을 위한 백삼 추출물 조제 연구)

  • Lee, Seung Eun;Kim, Geum Sook;Lee, Dae Young;Kim, Hyung Don;Lee, Jae Won;Lee, Young Sup;Park, Chun Geun;Ahn, Young Sup
    • Korean Journal of Medicinal Crop Science
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    • v.24 no.5
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    • pp.375-385
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    • 2016
  • Background: The study was conducted to elucidate the extraction conditions under which white ginseng has cognition-improving efficacy. Methods and Results: Extracts from white ginseng under different solvent and temperature conditions were analyzed for ginsenoside content and inhibitory effect on N-methyl-D-aspartate (NMDA) receptor and acetylcholinesterase. The total ginsenoside contents and amounts of ginsenoside Rb1 plus ginsenoside Rg1 from the 1st extracts (prepared with EtOH/$H_2O$ as solvent) were higher than those from the 2nd extracts (extracted with $H_2O$ after the 1st EtOH/$H_2O$ extraction). The contents in the 1st and 2nd extracts produced at $80^{\circ}C$ were also higher than those obtained at $50^{\circ}C$. Samples from the 1st extraction at $80^{\circ}C$ indicated higher inhibitory activities on NMDA receptors-whose excessive activation is thought to mediate the calcium-dependent neurotoxicity associated with several neurodegenerative diseases-than those from the 2nd extraction. Among the samples prepared at varying temperatures, the extract prepared at $50^{\circ}C$ showed the highest suppression activity on NMDA receptors. Note, however, that the extracts from the 2nd extraction at $50^{\circ}C$ inhibited acetylcholinesterase-whose inhibition could be a therapeutic strategy for neurodegenerative diseases with cognitive deficits and memory malfunction-more effectively than those from the 1st extraction. Conclusions: To enhance the cognition-improving activity of white ginseng extract, it is suggested that the extracts be utilized after being combined the 1st extracts (made with EtOH/$H_2O$ solvent) and the 2nd extracts (prepared with $H_2O$) at low temperature.

Reliability improvement of an ion-measuring system using FET sensor array (FET 센서 어레이를 이용한 이온 측정 시스템의 신뢰도 개선)

  • Choi, Jung-Tae;Lee, Seung-Hyup;Kim, Young-Jin;Lee, Young-Chul;Cho, Byung-Woog;Sohn, Byung-Ki
    • Journal of Sensor Science and Technology
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    • v.8 no.4
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    • pp.341-346
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    • 1999
  • In general cases, compared with glass electrode, FET type electrolyte sensors have many advantages. But the drift, memory effect and the poor reproducibility of the FET type electrolyte sensor cause the decrease of the reliability in the measurement system. To improve the reliability, an ion-measuring system using FET type electrolyte sensor array with 8 sensors has been developed. Developed system employed the electronic switchs to connect a signal detecting circuit with 8 sensor array and the system can measure ion concentration of 4 different type electrolyte($H^+$, $Na^+$, $K^+$, $Ca^{2+}$). The signal processing algorithm with insertion sorting method was adopted to enhance the reliability. We measured 3 different ion($H^+$, $Na^+$, $K^+$) to evaluate the performance of developed system. The results show that the designed signal processing algorithm can reduce the error range in comparison with a simple arithmetic mean and the developed system has a good reliability over the previous single channel sensor system.

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A Validation Study on the Drive Ability Cognitive Assessment Tool of Elderly Drivers (고령자 운전능력 인지 검사 도구의 타당화 연구)

  • Cheong, Moon Joo;Lee, Young Mi;Seo, Puluna
    • The Journal of the Korea Contents Association
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    • v.20 no.3
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    • pp.298-308
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    • 2020
  • This study was designed to verify reliability and feasibility by analyzing elderly drivers' ability test tools for older drivers aged 65 or older, which were improved in 2018 and are currently being conducted by the Korea Highway Traffic Authority. Only those aged 65 or older who voluntarily applied to the elderly driving ability evaluation system implemented by the Seoul branch of the Korea Highway Traffic Authority. The research was conducted for about 50 days until Aug. 31, 2018, starting with the registration and inspection of the first study subjects. The analysis performed a correlation analysis with existing tools and cognitive testing tools (MMSE_K) to determine their feasibility and reliability as an improved tool in 2018. As a result, the first, the speed distance, time-space memory, and dispersionism of each sub-component of the old version showed statistically significant static correlation with the sub-factor of the current version. Persistence, on the other hand, was not statistically significant to the current version. The limitations of this study were as follows. Most of the people in the study were highly educated and residents in the metropolitan area. Therefore, it is likely that the results of MSE_K, which checks cognitive and judgment skills, have been upgraded. Also, cognitive tools that are measured by computers are likely to have real measurement errors for generations who are not familiar with computers. Therefore, it is expected that improvement and development of tools for improving the limit points at the site and assessing actual operation capability will be required.

A Novel Cooperative Warp and Thread Block Scheduling Technique for Improving the GPGPU Resource Utilization (GPGPU 자원 활용 개선을 위한 블록 지연시간 기반 워프 스케줄링 기법)

  • Thuan, Do Cong;Choi, Yong;Kim, Jong Myon;Kim, Cheol Hong
    • KIPS Transactions on Computer and Communication Systems
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    • v.6 no.5
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    • pp.219-230
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    • 2017
  • General-Purpose Graphics Processing Units (GPGPUs) build massively parallel architecture and apply multithreading technology to explore parallelism. By using programming models like CUDA, and OpenCL, GPGPUs are becoming the best in exploiting plentiful thread-level parallelism caused by parallel applications. Unfortunately, modern GPGPU cannot efficiently utilize its available hardware resources for numerous general-purpose applications. One of the primary reasons is the inefficiency of existing warp/thread block schedulers in hiding long latency instructions, resulting in lost opportunity to improve the performance. This paper studies the effects of hardware thread scheduling policy on GPGPU performance. We propose a novel warp scheduling policy that can alleviate the drawbacks of the traditional round-robin policy. The proposed warp scheduler first classifies the warps of a thread block into two groups, warps with long latency and warps with short latency and then schedules the warps with long latency before the warps with short latency. Furthermore, to support the proposed warp scheduler, we also propose a supplemental technique that can dynamically reduce the number of streaming multiprocessors to which will be assigned thread blocks when encountering a high contention degree at the memory and interconnection network. Based on our experiments on a 15-streaming multiprocessor GPGPU platform, the proposed warp scheduling policy provides an average IPC improvement of 7.5% over the baseline round-robin warp scheduling policy. This paper also shows that the GPGPU performance can be improved by approximately 8.9% on average when the two proposed techniques are combined.