• 한국정밀공학회지
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• 제24권10호
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• pp.46-53
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• 2007

This paper describes the development of a high-precision measuring device with DSP (digital signal processor) for the accurate measurement of the 6-axis force/moment sensor mounted to a humanoid robot's ankle. In order to walk on uneven terrain safely, the foot should perceive the applied forces Fx, Fy, and Fz and moments Mx, My, and Mz to itself, and control the foot using the measured them. The applied forces and moments should be measured from two 6-axis force/moment sensors mounted to the feet, and the sensor is composed of Fx sensor, Fy sensor, Fz sensor, Mx sensor, My sensor and Mz sensor in a body (single block). In order to acquire output values from twelve sensors (two 6-axis force/moment sensor) accurately, the measuring device should get the function of high speed, and should be small in size. The commercialized measuring devices have the function of high speed, unfortunately, they are large in size and heavy in weight. In this paper, the high-precision measuring device for acquiring the output values from two 6-axis force/moment sensors was developed. It is composed of a DSP (150 MHz), a RAM (random access memory), amplifiers, capacities, resisters and so on. And the characteristic test was carried out.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2010년도 임시총회 및 하계학술연구발표회
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• pp.15-16
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• 2010

• 천문학회보
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• 제43권1호
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• pp.70.3-70.3
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• 2018

외계행성 탐색시스템의 망원경-카메라 제어 시스템 및 소프트웨어 구성과 관측 유틸리티에 대해 소개한다. 망원경 제어 소프트웨어는 천문 위치보정, 포인팅, 돔 회전 등을 담당하는 PC-TCS 프로그램, 망원경 적경-적위 축 서보 제어를 담당하는 full-closed loop PID 컨트롤 프로그램, 포커서, 필터박스, 돔 셔터, 주경냉각, 온도 모니터 등의 보조 시스템을 제어하는 AUX controls 프로그램으로 구성된다. 카메라 제어 소프트웨어는 모자이크로 구성된 여러 CCD를 각각 독립적으로 제어하는 IC(Instrument Control) 패키지와 이들을 총괄 제어하는 ICS(IC Science) 패키지로 구성되며 망원경과 카메라 소프트웨어의 인터페이스 역할을 하는 TCS Agent 프로그램이 포함된다. 관측 진행을 돕는 유틸리티로서 관측제어 명령어 입력 및 관측 스크립트 구동 기능을 제공하는 OBS Agent 프로그램과 가이드 CCD를 이용한 시상 모니터링 및 자동초점조정 프로그램을 개발하여 활용하고 있다. 각 소프트웨어는 UDP, TCP/IP, RS-232, Redis server 등 다양한 인터페이스를 통하여 서로 통신하며, CCD 영상 자료 전달을 위해 RAM(Random Access Memory) 디스크와 Network File System(NSF)을 이용하고 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.13-17
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• 2004

The PZT thin films are well-known material that has been widely studied for ferroelectric random access memory (FRAM). We etched the PZT thin films by $CF_4/(Cl_2+Ar)$ plasma and investigated improvement in etching damage by $O_2$ annealing. PZT thin films were etched for 1 min in an ICP using a gas mixture of $Cl_2$(80%)/Ar (20%) with 30% $CF_4$ addition. The etching conditions were fixed at a substrate temperature of $30^{\circ}C$, an rf power of 700 W, a dc-bias voltage of -200 V and a chamber pressure of 2 Pa. To improve the ferroelectric properties of PZT thin films after etching, the samples were annealed for 10 min at various temperatures in $O_2$ atmosphere. After $O_2$ annealing, the remanent polarization, fatigue, and the leakage current were gradually recovered to the characteristics of the as-deposited film, according as the temperature increased.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 추계학술대회 논문집 전기물성,응용부문
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• pp.87-89
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• 2005

$Bi_{3.25}Y_{0.75}Ti_{3}O_{12}$[BYT] ferroelectric thin films were deposited by RF-Sputtering method on the $Pt/Ti/SiO_2/Si$. We investigated the effects of processing condition (especially post-annealing) on the structural and ferroelectric properties of the BYT thin films. Increasing the annealing temperature, the peak intensity of (117) increased and c-axis orientation decreased. The BYT thin films crystallized well at $600^{\circ}C$ for 30min. No secondary phases observed in the XRD pattern. At annealing temperature of $700^{\circ}C$, the thin films had no cracks and the grain was uniform. The calculated lattice constants of BYT thin films were a=0.539nm, b=0.536nm, c=3.288nm. The remnant polarization of the $Bi_{3.25}Y_{0.75}Ti_{3}O_{12}$ capacitor reached $1.8uC/cm^2$ at an applied field about 400kV/cm. The BYT thin films can be used as capacitors in Ferroelectric Random Access Memory device.

• Journal of Computing Science and Engineering
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• 제7권1호
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• pp.53-66
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• 2013

Bounding the worst-case DRAM performance for a real-time application is a challenging problem that is critical for computing worst-case execution time (WCET), especially for multicore processors, where the DRAM memory is usually shared by all of the cores. Typically, DRAM commands from consecutive DRAM accesses can be pipelined on DRAM devices according to the spatial locality of the data fetched by them. By considering the effect of DRAM command pipelining, we propose a basic approach to bounding the worst-case DRAM performance. An enhanced approach is proposed to reduce the overestimation from the invalid DRAM access sequences by checking the timing order of the co-running applications on a dual-core processor. Compared with the conservative approach, which assumes that no DRAM command pipelining exists, our experimental results show that the basic approach can bound the WCET more tightly, by 15.73% on average. The experimental results also indicate that the enhanced approach can further improve the tightness of WCET by 4.23% on average as compared to the basic approach.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.201-201
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• 2010

DRAM (dynamic random access memory)은 하나의 트랜지스터와 하나의 캐패시터의 구조 (1T/1C)를 가지는 구조로써 빠른 동작 속도와 고집적에 용이하다. 하지만 고집적화를 위해서는 최소한의 캐패시터 용량 (30 fF/cell)을 충족시켜 주어야 한다. 이에 따라 캐패시터는 stack 혹은 deep trench 구조로 제작되어야 한다. 위와 같은 구조로 소자를 구현할 시 제작공정이 복잡해지고 캐패시터의 집적화에도 한계가 있다. 이러한 문제점을 보완하기 위해 1T-DRAM이 제안되었다. 1T-DRAM은 하나의 트랜지스터로 이루어져 있으며 SOI (silicon-on-insulator) 기판에서 나타나는 floating body effect를 이용하여 추가적인 캐패시터를 필요로 하지 않는다. 하지만 SOI 기판을 이용한 1T-DRAM은 비용측면에서 대량생산화를 시키기는데 어려움이 있으며, 3차원 적층구조로의 적용이 어렵다. 하지만 다결정 실리콘을 이용한 기판은 공정의 대면적화가 가능하고 비용적 측면에서 유리한 장점을 가지고 있으며, 적층구조로의 적용 또한 용이하다. 본 연구에서는 ELA (eximer laser annealing) 방법을 이용하여 비정질 실리콘을 결정화시킨 기판에서 1T-DRAM을 제작하였다. 하지만 다결정 실리콘은 단결정 실리콘에 비해 저항이 크기 때문에, 메모리 소자로서 동작하기 위해서는 높은 바이어스 조건이 필요하다. 게이트 산화막이 얇은 경우, 게이트 산화막의 열화로 인하여 소자의 오작동이 일어나게 되고 게이트 산화막이 두꺼울 경우에는 전력소모가 커지게 된다. 그러므로 메모리 소자로서 동작 할 수 있는 최적화된 게이트 산화막 두께가 필요하다. 제작된 소자는 KrF-248 nm 레이저로 결정화된 ELA 기판위에 게이트 산화막을 10 nm, 20 nm, 30 nm 로 나누어서 증착하여, 전기적 특성 및 메모리 특성을 평가하였다.

• 한국실내디자인학회논문집
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• 제22권5호
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• pp.143-151
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• 2013

As we recognize the space, humans will experience a process to synthesize elements of cognitive various methods, come to understand the environment. It is intended that on humans to recognize the space, it is intended to act directly under study how to recognize. Humans can know that the determining action based on the values and physical condition, based on the space in which they have been recognized, there are differences in the behavior of the human as a result. Social and arrangement of components - physical region that is cultural difficulties constitute experience specific areas therein. Space for human activities and human, can know that it is not a memory of human behavior, to have a closer relationship with human perception. That is, the description will be aware of the space via the perceptual phenomenon of man due to physical elements performed in the space, what acts about what happens. Through an understanding of the potential for this, and emotion space production consisting only of physical visual element future, and use act of the area to be expressed from his recognition, through the expansion of the perceptual elements, diverse experience richer and more it is a case where deemed necessary access space configuration capable of a broad depth study of this portion is happening, in order to constitute a space, a new interpretation for human behavior is progressing.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권3호
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• pp.111-115
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• 2006

We investigated accelerated soft error rate(ASER) in 8M static random access memory(SRAM) cells. The effects on ASER by well structure, operational voltage, and cell transistor threshold voltage are examined. The ASER decreased exponentially with respect to operational voltage. The chips with buried nwell1 layer showed lower ASER than those either with normal well structure or with buried nwell1 + buried pwell structure. The ASER decreased as the ion implantation energy onto buried nwell1 changed from 1.5 MeV to 1.0 MeV. The lower viscosity of the capping layer also revealed lower ASER value. The decrease in the threshold voltage of driver or load transistor in SRAM cells caused the increase in the transistor on-current, resulting in lower ASER value. We confirmed that in order to obtain low ASER SRAM cells, it is necessary to also the buried nwell1 structure scheme and to fabricate the cell transistors with low threshold voltage and high on-current.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2006년도 춘계학술대회 논문집
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• pp.417-418
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• 2006

CATIA V5 is one of the most preferred softwares in product design for domestic and industrial use. But with the development of the IT industry, design data by CATIA V5 can easily be hacked and stolen especially via the internet and through assistance storage medium. The design data could be protected through executive, physical and technical security system. The best way to maintain confidentiality of data from unauthorized access is to have a cryptosystem of the technical security. In this paper, a cryptosystem for the protection of design data was being proposed. The memory contains the file information made by the New and Open function of CATIA V5. No error can be expected even if the file changed before of after the application of Save and Open function, A cryptosystem was constructed in CATIA V5 by inserting crypto algorithm before and after the I/O process. The encryption/decryption algorithm of each function was based on the complex cipher, which applied permutation cipher and transpose cipher. The file security system was programmed in CAA V5 and Visual C++.