• Journal of Digital Contents Society
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• v.14 no.2
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• pp.247-254
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• 2013

Storage Class Memory(SCM), such as PRAM, FRAM and MRAM, are expected to be comparable to DRAM in terms of access speed and to Flash memory in terms of capacity in a near future. In this paper, assuming that not only the secondary storage (HDD or Flash memory) but also the primary memory (DRAM) will be replaced by SCM in the future computer systems, we propose an efficient file access framework for the SCM based computer systems. The proposed framework do not assign exclusive area in the SCM to the file system and uses various memory-related techniques, such as unified data access path, zero-copy data read using file mapping, copy-on-write, and multiple page pre-faulting for file management. Based on the preliminary experimental results, we could conclude that the proposed framework can be an efficient baseline for designing a new operating system for the SCM based computer systems.

• Journal of IKEEE
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• v.25 no.1
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• pp.180-192
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• 2021

One widely used algorithm for image recognition and pattern detection is the convolution neural network (CNN). To efficiently handle convolution operations, which account for the majority of computations in the CNN, we use hardware accelerators to improve the performance of CNN applications. In using these hardware accelerators, the CNN fetches data from the off-chip DRAM, as the massive computational volume of data makes it difficult to derive performance improvements only from memory inside the hardware accelerator. In other words, data communication between off-chip DRAM and memory inside the accelerator has a significant impact on the performance of CNN applications. In this paper, a simulator for the CNN is developed to analyze the main memory or DRAM access with respect to the size of the on-chip memory or global buffer inside the CNN accelerator. For AlexNet, one of the CNN architectures, when simulated with increasing the size of the global buffer, we found that the global buffer of size larger than 100kB has 0.8x as low a DRAM access count as the global buffer of size smaller than 100kB.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1209-1212
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• 2003

In this paper, we propose a SDRAM Controller. The SDRAM is often used a mainstream memory as embedded system memory due to its short latency, burst access and pipeline features. The proposed Controller provides essential functions for SDRAM initialization, read/write accesses, memory refresh and Burst access. Furthermore, the proposed controller is implemented in the form of SOFT IP. Therefore, it reduces the designer's effort greatly.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.743-744
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• 2006

This paper presents implementation of parallel processing system for image processing. The parallel processing system proposed consisted of 16 processing elements, and multi-access memory system, and interface modules. The multi-access memory system we introduced is made up of a memory module selection, a data routing module, and an address calculation and routing module.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.63-66
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• 2004

The extraordinary intrinsic properties of SiC have made this material a suitable choice to use in high temperature, high frequency, and high voltage applications. In additional to these, SiC could be employed as the based material for nonvolatile memory applications, mainly due to its extremely low thermal-generation rate at room temperature. In this paper, the reasons of using this material in this particular application is presented and the development of the application over the past fifteen years is reviewed.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.3_4
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• pp.187-194
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• 2004

Shear-Warp volume rendering has many advantages such as good image Quality and fast rendering speed. However in the interactive classification environment it has low efficiency of memory access since preprocessed classification is unavailable. In this paper we present an algorithm using the spacial locality of memory access in the interactive classification environment. We propose an extension model appending a rotation matrix to the factorization of viewing transformation, it thus performs a scanline-based rendering in the object and image space. We also show causes and solutions of three problems of the proposed algorithm such as inaccurate front-to-back composition, existence of hole, increasing computational cost. This model is efficient due to the spacial locality of memory access.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.335-344
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• 2014

In this paper we analysis for in out signal by previous study and implement virtual master that generate CGH processor signals. Also, we propose memory address mapping. By constructing the system model of our method and by analyzing the latencies according to the memory access methods in a system including our model and several other models, the low-latency memory access method has been obtained. The proposed method is reduce number of activation in DRAM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.101-109
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• 2009

Generally, depth cache and pixel cache of 3D graphics are designed by using write-back scheme for efficient use of memory bandwidth. Also, there are write after read operations of same address or only write operations are occurred frequently in 3D graphics cache. If a cache miss is detected, an access to the external memory for write back operation and another access to the memory for handling the cache miss are operated simultaneously. So on frequent cache miss situations, as the memory access bandwidth limited, the access time of the external memory will be increased due to memory bottleneck problem. As a result, the total performance of the processor or the IP will be decreased, also the problem will increase peak power consumption. So in this paper, we proposed a novel early write back cache architecture so as to solve the problems issued above. The proposed architecture controls the point when to access the external memory as to copy the valid data block. And this architecture can improve the cache performance with same hit ratio and same capacity cache. As a result, the proposed architecture can solve the memory bottleneck problem by preventing intensive memory accesses. We have evaluated the new proposed architecture on 3D graphics z cache and pixel cache on a SoC environment where ARM11, 3D graphic accelerator and various IPs are embedded. The simulation results indicated that there were maximum 75% of performance increase when using various simulation vectors.

• Journal of the Korea Society for Simulation
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• v.5 no.2
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• pp.25-40
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• 1996

Modeling of systems for intensive knowledge-based processing requires a modeling methodology that makes efficient access to the information in huge data base models. The proposed level access mothodology is a modeling approach applicable to systems where data is stored in a hierarchical and modular modules of active memory cells(processor/memory pairs). It significantly reduces the effort required to create discrete event simulation models constructed in hierarchical, modular fashion for above application. Level access mothodology achieves parallel access to models within the modular, hierarchical modules(clusters) by broadcasting the desired operations(e.g. querying information, storing data and so on) to all the cells below a certain desired hierarchical level. Level access methodology exploits the capabilities of object-oriented programming to provide a flexible communication paradigm that combines port-to-port coupling with name-directed massaging. Several examples are given to illustrate the utility of the methodology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.400-403
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• 2016

The resistive memory switching characteristics of resistive random access memory (ReRAM) using the amorphous GeSe thin film have been demonstrated at Al/Ti/GeSe/$n^+$ poly Si structure. This ReRAM indicated bipolar resistive memory switching characteristics. The generation and the recombination of chalcogen cations and anions were suitable to explain the bipolar switching operation. Space charge limited current (SCLC) model and Poole-Frenkel emission is applied to explain the formation of conductive filament in the amorphous GeSe thin film. The results showed characteristics of stable switching and excellent reliability. Through the annealing condition of $400^{\circ}C$, the possibility of low temperature process was established. Very low operation current level (set current: ~ ${\mu}A$, reset current: ~ nA) was showed the possibility of low power consumption. Particularly, $n^+$ poly Si based GeSe ReRAM could be applied directly to thin film transistor (TFT).