• The Journal of the Korea Contents Association
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• v.8 no.9
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• pp.27-33
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• 2008

This paper designs Shared Memory on the Dual Core system so that it operates a general System V IPC on the Linux O.S. Shared Memory is the technique that many processes can access to identical memory area. We treat Shared Memory which is SVR in a kernel step. We design a share memory facility of Linux operating system on the Dual Core System. In this paper the suggesting of share memory facility design plan in Dual Core system is enhance the performance in existing an unity processor system as a dual core practical use. We attemp a performance enhance in each CPU for each process which uses a share memory.

• KIISE Transactions on Computing Practices
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• v.21 no.8
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• pp.543-548
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• 2015

Recently, volume of data has been growing dramatically along with the growth of social media and digital devices. However, the existing disk-based distributed file systems have limits to their performance of data processing or data access, due to I/O processing costs and bottlenecks. To solve this problem, the caching technique is being used to manage data in the memory. In this paper, we propose a cache management scheme to handle load balancing in a distributed memory environment. The proposed scheme distributes the data according to the memory size, n distributed environments with different memory sizes. If overloaded nodes occur, it redistributes the the access time of the caching data. In order to show the superiority of the proposed scheme, we compare it with an existing distributed cache management scheme through performance evaluation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.765-768
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• 2001

A universal shipborne automatic identification system(AIS) uses self-organised time division multiple access(SOTDMA). The performance evaluation system of the SOTDMA algorithm for AIS is needed to implement it efficiently. This paper shows the method of designing it. Real ships access the VHF maritime mobile band but in this performance system, several ship objects access the shared memory. Real ships are designed as the object and the wireless communication channel is designed as the shared memory. This system shows several stations are assigned the transmission slot by the SOTDMA algorithm

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.390-390
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• 2012

Information technology industries has grown rapidly and demanded alternative memories for the next generation. The most popular random access memory, dynamic random-access memory (DRAM), has many advantages as a memory, but it could not meet the demands from the current of developed industries. One of highlighted alternative memories is magnetic random-access memory (MRAM). It has many advantages like low power consumption, huge storage, high operating speed, and non-volatile properties. MRAM consists of magnetic-tunnel-junction (MTJ) stack which is a key part of it and has various magnetic thin films like CoFeB, FePt, IrMn, and so on. Each magnetic thin film is difficult to be etched without any damages and react with chemical species in plasma. For improving the etching process, a high density plasma etching process was employed. Moreover, the previous etching gases were highly corrosive and dangerous. Therefore, the safety etching gases are needed to be developed. In this research, the etch characteristics of CoFeB magnetic thin films were studied by using an inductively coupled plasma reactive ion etching in $CH_4/O_2/Ar$ gas mixes. TiN thin films were used as a hardmask on CoFeB thin films. The concentrations of $O_2$ in $CH_4/O_2/Ar$ gas mix were varied, and then, the rf coil power, gas pressure, and dc-bias voltage. The etch rates and the selectivity were obtained by a surface profiler and the etch profiles were observed by a field emission scanning electron microscopy. X-ray photoelectron spectroscopy was employed to reveal the etch mechanism.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.387-387
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• 2013

Currently, the flash memory and the dynamic random access memory (DRAM) have been used in a variety of applications. However, the downsizing of devices and the increasing density of recording medias are now in progress. So there are many demands for development of new semiconductor memory for next generation. Magnetic random access memory (MRAM) is one of the prospective semiconductor memories with excellent features including non-volatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM is composed of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack consists of various magnetic materials, metals, and a tunneling barrier layer. Recently, MgO thin films have attracted a great attention as the prominent candidates for a tunneling barrier layer in the MTJ stack instead of the conventional Al2O3 films, because it has low Gibbs energy, low dielectric constant and high tunneling magnetoresistance value. For the successful etching of high density MRAM, the etching characteristics of MgO thin films as a tunneling barrier layer should be developed. In this study, the etch characteristics of MgO thin films have been investigated in various gas mixes using an inductively coupled plasma reactive ion etching (ICPRIE). The Cl2/Ar, CH3OH/Ar, and CH4/Ar gas mix were employed to find an optimized etching gas for MgO thin film etching. TiN thin films were employed as a hard mask to increase the etch selectivity. The etch rates were obtained using surface profilometer and etch profiles were observed by using the field emission scanning electron microscopy (FESEM).

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.341-351
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• 2003

For debugging effectively the shared-memory programs with nested parallelism, it is important to detect efficiently the first races which incur non-deterministic executions of the programs. Previous on-the-fly technique detects the first races in two passes, and shows inefficiencies both in execution time and memory space because the size of an access history for each shared variable depends on the maximum parallelism of program. This paper proposes a new on-the-fly technique to detect the first races in two passes, which is constant in both the number of event comparisons and the space complexity on each access to shared variable because the size of an access history for each shared variable is a small constant. This technique therefore makes on-the-fly race detection more efficient and practical for debugging shared-memory programs with nested parallelism.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.6
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• pp.454-459
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• 2020

In this study, a TiO₂/TiO_2-x-based resistance variable memory was fabricated using a DC/RF magnetron sputtering system and ALD. In order to analyze the effect of oxygen plasma treatment on the performance of resistance random access memory (ReRAM), the TiO₂/TiO_2-x-based ReRAM was evaluated by applying RF power to the TiO_2-x oxygen-holding layer at 30, 60, 90, 120, and 150 W, respectively. The ReRAM was fabricated, and the electrical and surface area performances were compared and analyzed. In the case of ReRAM without oxygen plasma treatment, the I-V curve had a hysteresis curve shape, but the width was very small, with a relatively high surface roughness of the oxygen-retaining layer. However, in the case of oxygen plasma treatment, the HRS/LRS ratio for the I-V curve improved as the applied RF power increased; stable improvement was also noted in the surface roughness of the oxygen-retaining layer. It was confirmed that the low voltage drive was not smooth due to charge trapping in the oxygen diffusion barrier layer owing to the high intensity ReRAM applied with an RF power of approximately 150 W.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.6A
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• pp.51-61
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• 2008

This paper suggests a new way to implement high speed AES on Intel Core2 processors and AMD Athlon64 processors, which are used all over the world today. First, Core2 Processors of EM64T architecture's memory-access-instruction processing efficiency are lower than calculus-instruction processing efficiency. So, previous AES implementation techniques, which had a high rate of memory-access-instruction, could cause memory-bottleneck. To improve this problem we present the partial round key techniques that reduce the rate of memory-access-instruction. The result in Intel Core2Duo 3.0 Ghz Processors show 185 cycles/block and 2.0 Gbps's throughputs in ECB mode. This is 35 cycles/block faster than bernstein software, which is known for being the fastest way. On the other side, in AMD64 processors of AMD64 architecture, by removing bottlenecks that occur in decoding processing we could improve the speed, with the result that the Athlon64 processor reached 170 cycles/block. The result that we present is the same performance of Matsui's unpublished software.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.81-92
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• 1995

In this paper, we present a high-level synthesis system that generates area-efficient RT-level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps , and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. Experimental results show the effectiveness of the proposed algorithm. When compared with previous approaches for several benchmarks available from literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.