• Korean Journal of Biological Psychiatry
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• v.8 no.1
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• pp.131-139
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• 2001

This study was conducted to evaluate the effect of PTSD on memory function and hippocampal volume, and to identify major variables correlated to hippocampal volume and memory function. Thirty four Vietnam veterans were collected for this study, among whom eighteen were PTSD patients and sixteen were combat control subjects. The author used Impact of Event Scale(IES), Combat Exposure Scale(CES), Hamilton Depression Rating Scale(HDRS) and Beck Depression Inventory (BDI). Korea Memory Assessment Scale(K-MAS) was assessed for memory function. Magnetic resonance imaging(MRI) was used to measure hippocampal volume. There were significant differences between PTSD and Non-PTSD veterans in IES, HDRS and BDI. Significant difference was found in verbal memory and total memory of K-MAS between PTSD and Non-PTSD veterans. There was significant difference in hippocampal volume between PTSD and Non-PTSD veterans. Short term memory, verbal memory and total memory were positively correlated to hippocampal volume. Hippocampal volume was negatively correlated to IES, HDRS, and BDI. These results suggest that PTSD severity be associated with hippocampal atrophy and memory dysfunction. Reduced or smaller hippocampal volume may be preexisting risk factor for stress exposure or the development of PTSD on combat exposure.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.457-464
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• 2005

In this paper a 3D memory system that allows 17 access types at an arbitrary position is introduced. The proposed memory system is based on two main functions: memory module assignment function and address assignment function. Based on them, the memory system supports 17 access types: 13 Lines, 3 Rectangles, and 1 Hexahedron. That is, the memory system allows simultaneous access to multiple data in any access types at an arbitrary position with a constant interval. In order to allow 17 access types the memory system consists of memory module selection circuitry, data routing circuitry for READ/WRITE, and address calculation/routing circuitry In the point of view of a developer and a programmer, the memory system proposed in this paper supports easy hardware extension according to the applications and both of them to deal with it as a logical three-dimensional away In addition, multiple data in various across types can be simultaneously accessed with a constant interval. Therefore, the memory system is suitable for building systems related to ,3D applications (e.g. volume rendering and volume clipping) and a frame buffer for multi-resolution.

• Journal of Information Processing Systems
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• v.15 no.1
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• pp.151-158
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• 2019

With the recent advances of memory technologies, high-performance non-volatile memories such as non-volatile dual in-line memory module (NVDIMM) have begun to be used as an addition or an alternative to server-side storages. When these memory bus-connected storages (MBSs) are installed over non-uniform memory access (NUMA) servers, the distance between NUMA nodes and MBSs is one of the crucial factors that influence file processing performance, because the access latency of a NUMA system varies depending on its distance from the NUMA nodes. This paper presents the design and implementation of a high-performance logical volume manager for MBSs, called MBS-LVM, when multiple MBSs are scattered over a NUMA server. The MBS-LVM consolidates the address space of each MBS into a single global address space and dynamically utilizes storage spaces such that each thread can access an MBS with the lowest latency possible. We implemented the MBS-LVM in the Linux kernel and evaluated its performance by porting it over the tmpfs, a memory-based file system widely used in Linux. The results of the benchmarking show that the write performance of the tmpfs using MBS-LVM has been improved by up to twenty times against the original tmpfs over a NUMA server with four nodes.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1102-1107
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• 1988

We describe a volume holographic associative memory using photorefractive material and conventional planar mirror. Multiple hologram is generated with two angular multiplexed writing beams and Fourier transformed object beam in Ba Ti O3 crystal at 0.6328 um. Complete image can be recalled successfully by partial input of the original stored image without any additional thresholding and optical feedback process. It is proved that our system is useful for optical implementation of real-time associative memory and location addressable memory.

• Transactions of Materials Processing
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• v.18 no.1
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• pp.45-51
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• 2009

Shape memory alloy has been used to improve the tensile strength of composite by the occurrence of compressive residual stress in matrix using its shape memory effect. In order to fabricate shape memory alloy composite, TiNi alloy fiber and Al2024 sheets were used as reinforcing material and matrix, respectively. In this study, TiNi/Al2024 shape memory alloy composite was made by using hot press method. In order to investigate bonding condition between TiNi reinforcement and Al matrix, the micro-structure of interface was observed by using optical microscope and diffusion layer of interface was measured by using Electron Probe Micro Analyser. And the mechanical properties of composite with three parameters(volume fraction of fiber, cold rolling amount and test temperature) were obtained by tensile test. The most optimum bonding condition for fabrication the TiNi/Al2024 composite material was obtained as holding for 30min. under the pressure of 60MPa at 793K. The strength of composite material increased considerably with the volume fraction of fiber up to 7.0%. And the tensile strength of this composite increased with the reduction ratio and it also depends on the volume fraction of fiber.

• Journal of Korea Spatial Information System Society
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• v.11 no.2
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• pp.79-88
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• 2009

The volume of memory to store real-time data stream is varied dynamically. Continuous queries processing the data stream must manage the storage volume dynamically. In previous research, according to current volume of data a general memory manager which allocates and releases memory by a page unit is researched.However, the method frequently executes page allocation and release to store data stream. Moreover, particularly delayed queries can monopolize many of pages because the method directly allocates pages when a query has not enough memory. Focusing on the problems in memory management systems, this research proposes a memory management method which reduces the frequency of allocation and release and uniformly distributes pages for queries. The method can reduce the frequency of allocation and release through allocation based on utilization ratio of pages in each query and prevent memory monopoly through memory allocation which considers query delay.

• Journal of the Korea Computer Graphics Society
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• v.23 no.3
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• pp.19-29
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• 2017

When a fixed-sized memory allocation method is used for sparse volume data, a considerable memory space is in general wasted, which becomes more serious for a large volume of high resolution. In this paper, in order to reduce such unnecessary memory consumption, we propose a volume representation method to store mostly voxels that represent valid information rather than all voxels in a fixed volume space. Then our method is compared with the conventional static memory allocation method, an octree-based representation, and a voxel hashing method in terms of memory usage and computation speed. In particular, we compare the proposed method and the voxel hashing method with respect to implementation of the GPU-based Marching Cubes algorithm.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.28-39
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• 1994

We experimented on memory multichip modules to increase the packing density of memory devices and to improve their electrical characteristics. A 128K$\times$8bit SRAM module was made of four 32K$\times$8bit SRAM memory chips. The memory multichip module was constructed on a low-cost double sided PCB(printed circuit boared) substrate. In the process of fabricating a multichip module. we focused on the improvement of its electrical characteristics. volume, and weight by employing bare memory chips. The characteristics of the bare chip module was compared with that of the module with four packaged chips. We conducted circuit routing with a PCAD program, and found the followings: the routed area for the module with bare memory chips reduced to a quarter of that area for module with packaged memory chips. 1/8 in volume, 1/5 in weight. Signal transmission delay times calculated by using transmission line model was reduced from 0.8 nsec to 0.4 nsec only on the module board, but the coupling coefficinet was not changed. Thus, we realized that the electrical characteristics of multichip packages on PCB board be improved greatly when using bare memory chips.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.22 no.3
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• pp.624-634
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• 1998

The photoelastic model material with shape memory effect and the molding processes for the material are developed in this research. The matrix and fiber of the photoelastic model material developed in this research are epoxy resin (Araldite to hardner 10 to 3 (weight ratio)) and wire of $Ti_50-Ni_50$ shape memory alloy, respectively. It is called Ti50-Ni50 Shape Memory Alloy Fiber Epoxy Composite $(Ti_50-Ni_50SMA-FEC).$ Ti50-Ni50 SMA-FEC is satisfied with the requirements of the photoelastic model material and can be used as a photoelastic model material. The maximum recovering strain of $Ti_50-Ni_50$SMA-FEC is occurred at $80^{\circ}C$ in any prestrain of $Ti_50-Ni_50$ shape memory alloy fiber and in any fiber volume ratio. Recovering strain(force) is increased with the increment of the prestrain and the fiber volume ratio. The best prestrain of $Ti_50-Ni_50$SMA-FEC is 5% for the recovering force among 1%, 3%, 5%.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.9
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• pp.1-8
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• 2017

The purpose of this study is to propose a cache structure for processing large-volume building information modeling (BIM) geometry data,whereit is difficult to allocate physical memory. As the number of BIM orders has increased in the public sector, it is becoming more common to visualize and calculate large-volume BIM geometry data. Design and review collaboration can require a lot of time to download large-volume BIM data through the network. If the BIM data exceeds the physical free-memory limit, visualization and geometry computation cannot be possible. In order to utilize large amounts of BIM data on insufficient physical memory or a low-bandwidth network, it is advantageous to cache only the data necessary for BIM geometry rendering and calculation time. Thisstudy proposes acache structure for efficiently rendering and calculating large-volume BIM geometry data where it is difficult to allocate enough physical memory.