• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.330-338
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• 2016

Phase change memory (PCM) has been studied as an emerging memory technology for last-level cache (LLC) due to its extremely low leakage. However, it consumes high levels of energy in updating cells and its write endurance is limited. To relieve the write pressure of LLC, we propose a delta value indicator (DVI) by employing a small cache which stores the difference between the value currently stored and the value newly loaded. Since the write energy consumption of the small cache is less than the LLC, the energy consumption is reduced by access to the small cache instead of the LLC. In addition, the lifetime of the LLC is further extended because the number of write accesses to the LLC is decreased. To this end, a delta value indicator and controlling circuits are inserted into the LLC. The simulation results show a 26.8% saving of dynamic energy consumption and a 31.7% lifetime extension compared to a state-of-the-art scheme for PCM.

• 한국멀티미디어학회논문지
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• 제21권2호
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• pp.232-241
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• 2018

Operational Transformation (OT) algorithms for real-time collaborative editing systems are becoming increasingly important due to the increased demand for collaborative data processing. The operational transformation algorithm is a technique for real-time concurrency control and consistency maintenance with non-locking technique, and many studies have been conducted to overcome three issues of convergence, causality-prevention, and intention-prevention. However, previous work has the disadvantage of wasting memory by storing all operations that occurred during an edit operation in the history buffer to solve this problem. Therefore, we propose a memory-saving real-time collaborative editing system that maintains a constant memory space and concurrency control through a method of applying the valid-time to each user-generated operation in order to reduce memory waste. This system prevents long-term memory occupation of client-generated operations, thus it reduces the space and time complexity even with low-rate of collaboration work, so that the performance degradation avoids.

• 한국컴퓨터정보학회논문지
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• 제15권3호
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• pp.1-10
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• 2010

프로세서 플랫폼이 무선의 모바일 시스템으로 변화하면서 내장형 모바일 프로세서들의 성능은 계속적으로 향상 되었으며 기능은 보다 더 강력해 지고 있다. 무선의 휴대용 장비들은 유선 장비에 비해 휴대용 전원에 의한 제한된 전력을 공급받기 때문에, 이러한 시스템들에 대한 효율적 에너지 관리 기술의 중요성은 점차 증가하고 있다. 한편, 메모리 시스템은 프로세서 관점에서 시스템 전체의 성능을저하 시키는 주된 요소 가운데 하나이다. 비록 휴대용 전원의 효과적 활용을 위한 DVFS 기법과 관련된 많은 연구들이 존재하지만, 프로세서와 메모리 사이의 상호 관계에 대한 최근의 연구는 부족한 실정이다. 본 연구에서는 무선의 모바일 장치들에서 활용되는 내장형 응용 프로그램의 장단기 메모리 접근 특성을 반영하기 위한 새로운 DVFS 레벨 예측 알고리즘을 소개한다. 모의 실험 결과 본 논문에서 제시하는 DVFS 정책은 메모리 접근이 많은 벤치마크 프로그램의 경우 5.86%의 소비 에너지 감소 효과를 보여주고 있으며, 평균적으로는 3.60%의 소비 에너지 감소 효과를 보여주고 있다.

• 대한임베디드공학회논문지
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• 제5권2호
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• pp.77-83
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• 2010

In this paper, we propose an efficient memory architecture for coeff_token encoding in H.264/AVC standard. The VLCTs used to encode the coeff_token syntax element are implemented with the memory. In general, the size of memory must be reduced because it affects the cost and operation speed of the system. Based on the analysis for the codewords in VLCTs, new memory architecture is designed in this paper. The proposed memory architecture results in about 24% memory saving, compared to the conventional memory architecture.

• International Journal of Internet, Broadcasting and Communication
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• 제14권1호
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• pp.188-193
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• 2022

The energy efficiency of memory systems is an important task in designing future computer systems as memory capacity continues to increase to accommodate the growing big data. In this article, we present an energy-efficient last-level cache management policy for future mobile systems. The proposed policy makes use of low-power PCM (phase-change memory) as the main memory medium, and reduces the amount of data written to PCM, thereby saving memory energy consumptions. To do so, the policy keeps track of the modified cache lines within each cache block, and replaces the last-level cache block that incurs the smallest PCM writing upon cache replacement requests. Also, the policy considers the access bit of cache blocks along with the cache line modifications in order not to degrade the cache hit ratio. Simulation experiments using SPEC benchmarks show that the proposed policy reduces the power consumption of PCM memory by 22.7% on average without degrading performances.

• 한국인터넷방송통신학회논문지
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• 제21권6호
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• pp.71-76
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• 2021

최근 사물인터넷의 데이터가 대용량화됨에 따라 실시간 시스템의 메모리 전력 소모가 급증하고 있다. 이는 실시간 시스템이 태스크 전체를 항상 메모리에 올려놓고 처리함으로 인한 DRAM 용량 증가에 기인한다. 본 논문은 최근 각광 받는 고속 스토리지를 활용하여 실시간 태스크의 일부를 스토리지에 내려놓고 필요시 메모리에 올리는 전력 절감 기술을 제안한다. 또한, 이를 CPU의 동적 전압조절 기법과 결합하여 CPU와 메모리의 전력 절감을 동시에 최적화한다. 제안하는 기술은 CPU의 유휴시간을 최대한 줄이는 전압 모드를 결정하는 동시에 메모리 크기를 최소화하는 스왑 비율을 결정하여, 태스크의 데드라인을 어기지 않으면서 전력 소모를 최소화하는 최적의 조합을 탐색한다. 시뮬레이션 실험을 통해 제안하는 기술이 실시간 시스템의 전력 소모를 크게 줄임을 보인다.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2012년도 추계학술대회
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• pp.52-53
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• 2012

Belief propagation (BP) is a commonly used global energy minimization algorithm for solving stereo matching problem in 3D reconstruction. However, it requires large memory bandwidth and data size. In this paper, we propose a novel memory-efficient algorithm of BP in stereo matching on the Graphics Processing Units (GPU). The data size and transfer bandwidth are significantly reduced by storing only a part of the whole message. In order to maintain the accuracy of the matching result, the local messages are reconstructed using shared memory available in GPU. Experimental result shows that there is almost an order of reduction in the global memory consumption, and 21 to 46% saving in memory bandwidth when compared to the conventional algorithm. The implementation result on a recent GPU shows that we can obtain 22.8 times speedup in execution time compared to the execution on CPU.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.1580-1584
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• 1991

The purpose of the present study is to investigate, from the viewpoint of labor science, the effect of labor saving by crawler-type truck, which has been used for the rationalization of transportation labor in the citrus orchard on steep slops, and to find out how effectively to utilize the crawler-type truck. In order to attain the purpose mentioned above, portable heart rate memory for measuring physical response of laborer was taken, and the experiment was carried out in the citrus orchard on steep slopes in Japan.

• 한국인터넷방송통신학회논문지
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• 제20권1호
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• pp.135-140
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• 2020

최근 사물인터넷, 지능형 시스템 등의 활성화로 실시간 임베디드 시스템의 전력 절감 기술이 중요해지고 있다. 본 논문은 멀티코어 이기종메모리 환경에서 실시간 시스템의 전력 소모량을 절감하는 P-GA (parallel genetic algorithm) 스케줄링 알고리즘을 제안한다. P-GA는 멀티코어를 위한 PF (proportional fairness) 알고리즘에 기반한 프로세서의 전압 및 주파수 동적 조절 기법에 차세대 비휘발성메모리 기술을 결합하여 시스템의 전력 소모를 더욱 줄인다. 특히, 유전 알고리즘을 사용하여 태스크별 수행 프로세서의 전압 및 주파수 모드와 메모리의 종류를 최적화하여 태스크 집합의 전력 소모량을 최소화한다. 시뮬레이션 실험을 통해 P-GA가 기존 방식 대비 최대 2.85배의 전력 소모량을 감소할 수 있음을 보인다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2003년도 ISIS 2003
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• pp.640-643
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• 2003

A Walsh function based associative memory is capable of storing m patterns in a single pattern storage space with Walsh encoding of each pattern. Furthermore, each stored pattern can be matched against the stored patterns extremely fast using algorithmic parallel processing. As such, this special type of memory is ideal for real-time processing of large scale information. However this incredible efficiency generates large amount of crosstalk between stored patterns that incurs mis-recognition. This crosstalk is a function of the set of different sequencies [number of zero crossings] of the Walsh function associated with each pattern to be stored. This sequency set is thus optimized in this paper to minimize mis-recognition, as well as to maximize memory saying. In this paper, this Walsh memory has been applied to the problem of face recognition, where PCA is applied to dimensionality reduction. The maximum Walsh spectral component and genetic algorithm (GA) are applied to determine the optimal Walsh function set to be associated with the data to be stored. The experimental results indicate that the proposed methods provide a novel and robust technology to achieve an error-free, real-time, and memory-saving recognition of large scale patterns.