• The Journal of the Korea Contents Association
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• v.8 no.4
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• pp.48-54
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• 2008

This paper analyzes cost tradeoffs between memory usage and computation for window-based operators in data stream environments. It identifies generic operator network constructs, and sets up a cost model for the estimation of the expected memory reduction and the computation overheads when window memory relocations are applied to each operator network construct. This cost model helps to identify the utility of window memory relocations. It also helps to apply window memory relocation to improve a query execution plan to save memory usage. The proposed approach contributes to expand the scope of query processing and optimization in data stream environments. It also provides a basis to develop a cost estimation model for the query optimization using window memory relocations.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.12
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• pp.568-575
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• 2008

Server consolidation by sever virtualization can make one physical machine(PM) to run several virtual machines simultaneously. Although It is attractive in cost, it has complex workload behaviors. For that reason, efficient resource management method is required. Dynamic relocation of virtual machine(VM)[3,4] by live migration[1,2] is one of resource management methods. We proposed SCOA(Server Consolidation Optimizing Algorithm) : a fine-grained load balancing mechanism worked on this dynamic relocation mechanism. We could obtain accurate resource distribution information through pointed physical machines on multi dimensional resource usage coordination, so we could maintain more balanced resource state. In this paper, we show the effectiveness of our algorithm by comparison of experimental results between SCOA and sandpiper[3] by software simulation.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.40 no.8
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.841-843
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• 2005

최근 64비트 CPU의 시장 출시가 활발해지고 있으며, 메모리 모듈 또한 대용화가 이루어지고 있다. 이에 대용량 메모리를 64비트 CPU 플랫폼에서 효과적으로 테스트하는 방법을 개발할 필요성이 대두되고 있다. 본 논문에서는 x86-64 기반 리눅스 2.6.11 커널에서 물리 메모리의 테스트 영역을 확장하는 기법을 제안한다. 제안된 기법에는 응용이나 커널에서 물리 메모리에 대한 직접 접근, 프로그램을 사용자가 원하는 물리 메모리로 배치, 프로그램의 동적 재배치 등의 방법을 통해 테스트 영역을 확장 한다. 현재 64 비트 CPU를 지원하는 OS는 리눅스와 윈도우즈 64비트 에디션 등이 있다. 기존 리눅스 커널을 그대로 사용하였을 때 프로그램 등이 이미 사용 중인 물리 메모리에 대해서는 메모리 테스트를 수행 할 수 없었으나, 각 프로그램들을 물리 메모리에서 재배치하여, 원하는 곳의 메모리를 테스트 할 수 있도록 커널 수정을 통하여 구현하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.450-463
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• 2000

Array redistribution is usually required to enhance algorithm performance in many parallel programs on distributed memory multicomputers. GEN_BLOCK redistribution, which is redistribution between different GEN_BLOCKs, is essential for load balancing. However, prior research on redistribution has been focused on regular redistribution, such as redistribution between different CYCLIC(N)s. GEN_BLOCK redistribution is very different from regular redistribution. Message passing in regular redistribution involves repetitions of basic message passing patterns, while message passing for GEN_BLOCK redistribution shows locality. This paper proves that two optimal condition, reducing the number of communication steps and minimizing redistribution size, are essential in GEN_BLOCK redistribution. Additionally, by adding a relocation phase to list scheduling, we make an optimal scheduling algorithm for GEN_BLOCK redistribution. To evaluate the performance of the algorithm, we have performed experiments on a CRAY T3E. According to the experiments, it was proven that the scheduling algorithm shows better performance and that the conditions are critical in enhancing the communication speed of GEN_BLOCK redistribution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.8
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• pp.868-872
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• 2010

Many embedded Java systems are equipped with limited memory, which can constrain the code cache size provided for Java just-in-time compilation, affecting the Java performance. This paper proposes expanding the limited code cache when it is full, by saving the machine code for some methods in the code cache into the file system of the permanent storage and reloading it to the code cache when they are re-invoked later. This is applying the client ahead-of-time compilation during the execution time for the purpose of enlarging the code cache. Our experimental results indicate that the proposed execution method can improve the performance by as much as 1.6 times compared to the conventional method, when the code cache size is reduced by half.