• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.99-109
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• 1992

First, the coupling faults of semiconductor memory are classified in detail. The chained coupling fault is introduced and defined, which results from sequential influencing of the coupling effects among memory cells, and its mapping relation is described. The linked coupling fault and its order are defined. Second, the deterministic “Algorithm GA” is proposed, which detects stuack-at faults, transition faults, address decoder faults, unlinked 2-coupling faults, and unlinked chained coupling faults. The time complexity and the fault coverage are improved in this algorithm. Third, it is proved that the march test of an address sequence can detect 97.796% of the linked 2-coupling faults with order 2. The deterministic “Algorithm NA” proposed can detect to the limit. The time complexity and the fault coverage are improved in this algorithm.

• The Journal of Information Technology
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• v.10 no.4
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• pp.41-56
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• 2007

In Digital Computing Environment, volatile information such as register, cache memory, and network information are hard to make certain of a real-time collection because such volatile information are easily modified or disappeared. Thus, a collection of volatile information is one of important step for computer forensics system on ubiquitous computing. In this paper, we propose a volatile information collection module, which collects variable volatile information of server system based on memory mapping in real-time.

• Proceedings of the Korea Contents Association Conference
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• 2008.05a
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• pp.507-513
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• 2008

In Digital Contents Computing Environment, information such as register, cache memory, and network information are hard to make certain of a real-time collection because such information collection are easily modified or disappeared. Thus, a collection of information is one of important step for computer forensics system on Digital Contents computing. In this paper, we propose information collection module, which collects variable information of server system based on memory mapping in real-time.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2019.06a
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• pp.98-101
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• 2019

At present, deep convolutional neural networks have made a very important contribution in single-image super-resolution. Through the learning of the neural networks, the features of input images are transformed and combined to establish a nonlinear mapping of low-resolution images to high-resolution images. Some previous methods are difficult to train and take up a lot of memory. In this paper, we proposed a simple and compact deep recursive residual network learning the features for single image super resolution. Global residual learning and local residual learning are used to reduce the problems of training deep neural networks. And the recursive structure controls the number of parameters to save memory. Experimental results show that the proposed method improved image qualities that occur in previous methods.

• Proceedings of the Korea Information Processing Society Conference
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• 2013.11a
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• pp.81-82
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• 2013

바이트 단위로 접근이 가능하고, 비휘발성을 가지는 SCM(Storage Class Memory)을 이용하여 프로세스의 작업공간으로 활용함과 동시에 파일을 저장하는 형태의 운영체제 기법에 대한 연구가 활발하게 이루어지고 있다. 본 논문에서는 이러한 형태에서 파일이 저장되는 방법을 토대로 프로세스 생성 시 실행 파일의 읽기 전용의 특성을 가지는 실행 코드를 프로세스 공간에 직접 매핑하는 기법에 대하여 제안한다.

• Journal of the Korean Society for Precision Engineering
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• v.10 no.1
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• pp.77-88
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• 1993

In this paper, we propose a stereo vision system to solve correspondence problem with large disparity and sudden change in environment which result from small distance between camera and working objects. First of all, a specific feature is divided by predfined elementary feature. And then these are combined to obtain coded data for solving correspondence problem. We use Neural Network to extract elementary features from specific feature and to have adaptability to noise and some change of the shape. Fourier transformation and Log-polar mapping are used for obtaining appropriate Neural Network input data which has a shift, scale, and rotation invariability. Finally, we use associative memory to obtain coded data of the specific feature from the combination of elementary features. In spite of specific feature with some variation in shapes, we could obtain satisfactory 3-dimensional data from corresponded codes.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.828-831
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• 2008

플래시 메모리(Flash Memory) 기술이 빠르게 발전하면서, 플래시 메모리 기반의 저장 장치가 개인용 컴퓨터나 엔터프라이즈 서버 시스템과 같은 시스템에 2차적인 저장 장치로써 사용가능해지고 있다. FTL(Flash Translation Layer)의 기본적인 기능은 플래시 메모리의 논리 주소를 물리 주소로 바꾸는 것임에도 불구하고, FTL의 효율적인 알고리즘은 성능과 수명에 상당한 효과를 가지고 있다. 이 논문에서는 MP3 플레이어와 디지털 카메라, SSDs(Solid-State Disk)와 같은 낸드 플래시 메모리(NAND Flash Memory) 기반의 어플리케이션을 위한 N : N+K 매핑을 사용하는 새로운 FTL 설계를 제안한다. 성능에 영향을 미치는 매개변수들을 분류하여, 다양한 워크로드 분석을 기반으로 FTL을 조사했다. 우리가 제안하는 FTL을 가지고, 낸드 플래시 어플리케이션 가동에 따라 어떤 매개변수가 최대 성능을 낼 수 있는지 알아낼 수 있고, 그 변수들을 유연하게 조정하여 성능을 더 향상시킬 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1675-1689
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• 2000

We present CReMeS a CORBA-compliant design and implementation of a new real-time communication service. It provides for efficient predictable and scalable communication between information producers and consumers. The CReMeS architecture is based on MidART's Real-Time Channel-based Reflective Memory (RT-CRM) abstraction. This architecture supports the separation of QoS specification between producer and consumer of data and employs a user-level scheduling scheme for communicating real-time tasks. These help us achieve end-to-end predictability and allows our service to scale. The CReMeS architecture provides a CORBA interface to applications and demands no changes to the ORB layer and the language mapping layer. Thus it can run on non real-time Off-The-Shelf ORBs enables applications on these ORBs to have scalable and end-to-end predictable asynchronous communication facility. In addition an application designer can select whether to use an out-of-band channel or the ORB GIOP/IIOP for data communication. This permits a trade-off between performance predictability and reliability. Experimental results demonstrate that our architecture can achieve better performance and predictability than a real-time implementation of the CORBA Even Service when the out-of-band channel is employed for data communication it delivers better predictability with comparable performance when the ORB GIOP/IIOP is used.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.508-519
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• 2007

Flash memory based storage has been used in various mobile systems and now is to be used in Laptop computers in the name of Solid State Disk. The Flash memory has not only merits in terms of weight, shock resistance, and power consumption but also limitations like erase-before-write property. To overcome these limitations, Flash memory based storage requires special address mapping software called FTL(Flash-memory Translation Layer), which often performs merge operation for block recycling. In order to reduce block recycling cost in NAND Flash memory based storage, we introduce another block recycling scheme which we call migration. As a result, the FTL can select either merge or migration depending on their costs for each block recycling. Experimental results with Postmark benchmark and embedded system workload show that this cost-based selection of migration/merge operation improves the performance of Flash memory based storage. Also, we present a solution of macroscopic optimal migration/merge sequence that minimizes a block recycling cost for each migration/merge combination period. Experimental results show that the performance of Flash memory based storage can be more improved by the macroscopic optimization than the simple cost-based selection.