• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.236-236
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• 2008

(Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12C
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• pp.1175-1187
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• 2007

This paper proposes a novel crest factor reduction (CFR) algorithm to be deployed on WCDMA basestation. Generally speaking, it is well described that the reduction of peak-to-average ratio (PAR) yields the possibility of using low cost power amplifier such that the basesation becomes economic However, the simple reduction of PAR could degrade the signal quality measured by either peak code domain error (PCDE) or error vector measurement (EVM), and the level of channel interference constrained by adjacent channel leakage ratio (ACLR). Regarding these imperfections, this paper introduces an effective CFR algorithm in which the function of filter-dependent CFR (FDCFR) incorporated with the histogram-based waterfilling code domain compensation (HBWCDC) carries out. To verify the performance of the proposed CFR technique, substantial simulations including comparative works are conducted with obeying W-CDMA basestation verification specification. To exploit the superiority, the performance of the proposed method is tentatively compared with that associated to the simple memoryless clipping method and the memory-required filter-dependent clipping method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.77-83
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• 2004

In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.

• Journal of Internet of Things and Convergence
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• v.6 no.2
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• pp.93-100
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• 2020

Although various home services are developed as increasing the number of home devices with wire and wireless connection, privacy infringement and private information leakage are occurred by unauthorized remote connection. It is almost caused by without of device authentication and protection of transmission data. In this paper, the devices' secret value are stored in a safe memory of a smartphone. A smartphone processes device authentication. In order to prevent leakage of a device's password, a shadow password multiplied a password by the private key is stored in a device. It is proposed mutual authentication between a smartphone and a device, and session key agreement for devices using recovered passwords on SRP. The proposed protocol is resistant to eavesdropping, a reply attack, impersonation attack.

• Journal of Korea Game Society
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• v.15 no.1
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• pp.77-88
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• 2015

As the smart phone market is drastically expanding, there is a steady growth of recent vicious activities such as data manipulation, billing fraud, identity theft, and leakage of personal information that are security threats to Social Network Games(SNG). Due to the threats, Strong development standard is required for security enhancement of SNG. Nonetheless, short life-spans, additional expenses, and the necessities to provide a sound game service hinders developers from reaching their security goals. Therefore, this research investigates the weak points of SNG through memory manipulation experiments based on the currently provided SNG services. In addition, the research presents counter measures and security enforcements that are light in service load and simplistic which can be applied in the developing process.

• Journal of Power Electronics
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• v.11 no.2
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• pp.228-236
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• 2011

The ${\Delta}\;V_{10}$ or 10-Hz flicker index, as a common method of measurement of voltage flicker severity in power systems, requires a high computational cost and a large amount of memory. In this paper, for measuring the ${\Delta}\;V_{10}$ index, a new method based on the Adaline (adaptive linear neuron) system, the FFT (fast Fourier transform), and the PSO (particle swarm optimization) algorithm is proposed. In this method, for reducing the sampling frequency, calculations are carried out on the envelope of a power system voltage that contains a flicker component. Extracting the envelope of the voltage is implemented by the Adaline system. In addition, in order to increase the accuracy in computing the flicker components, the PSO algorithm is used for reducing the spectral leakage error in the FFT calculations. Therefore, the proposed method has a lower computational cost in FFT computation due to the use of a smaller sampling window. It also requires less memory since it uses the envelope of the power system voltage. Moreover, it shows more accuracy because the PSO algorithm is used in the determination of the flicker frequency and the corresponding amplitude. The sensitivity of the proposed method with respect to the main frequency drift is very low. The proposed algorithm is evaluated by simulations. The validity of the simulations is proven by the implementation of the algorithm with an ARM microcontroller-based digital system. Finally, its function is evaluated with real-time measurements.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.306.2-306.2
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• 2014

전자기기의 휴대성과 이동성이 강조되고 있는 현대사회에서 비휘발성 메모리는 메모리 산업에 있어 매우 매력적인 동시에 커다란 잠재성을 지닌다. 이미 공정의 한계에 부딪힌 Flash 메모리를 대신하여 10nm 이하의 공정이 가능한 상변화 메모리(Phase-Change Memory, PRAM), 스핀 주입 자화 반전 메모리(Spin Transfer Torque-Magnetic RAM, STT-MRAM), 저항 변화 메모리(Resistive Random Access Memory, ReRAM)가 차세대 비휘발성 메모리 후보로서 거론되고 있으며, 그 중에서도 ReRAM은 빠른 속도와 낮은 소비 전력, CMOS 공정 호환성, 그리고 비교적 단순한 3차원 적층 구조의 특성으로 인해 활발히 연구되고 있다. 특히 최근에는 질화물 또는 질소를 도핑한 산화물을 저항변화 물질로 사용하는 ReRAM이 보고되고 있는데, 이들은 동작전압이 낮을 뿐만 아니라 저항 변화(Resistive Switching, RS) 과정에서 일어나는 계면 산화를 방지할 수 있으므로 ReRAM의 저항 변화 재료로서 각광받고 있다. 그러나 Cell 단위의 ReRAM 소자를 Crossbar Array 구조에 적용시켰을 때 주변 Cell과의 저항 상태 차이로 인해 전류가 낮은 저항 상태(LRS)의 Cell로 흘러 의도치 않은 동작을 야기한다. 이와 같이 누설 전류(Leakage Current)로 인한 상호간의 간섭이 일어나는 Cross-talk 현상이 존재하며, 공정의 간소화와 집적도를 유지하면서 이 문제를 해결하는 것은 실용화하기에 앞서 매우 중요한 문제이다. 따라서, 본 논문에서는 Read 동작 시 발생하는 Cell과 Cell 사이의 Cross-talk 문제를 해결하기 위해 자가 정류 특성(Self-Rectifying)을 가지는 실리콘 질화물/알루미늄 질화물 이중층(Si3N4/AlN Bi-layer)으로 구성된 ReRAM 소자 구조를 제안하였으며, Sputtering 방법을 이용하여 제안된 소자를 제작하였다. 전압-전류 특성 실험결과, 제안된 구조에 대한 에너지 밴드 다이어그램 시뮬레이션 결과와 동일하게 Positive Bias 영역에서 자가 정류 특성을 획득하였고, 결과적으로 Read 동작 시 발생하는 Cross-talk 현상을 차단할 수 있는 결과를 확보하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.789-790
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• 2013

$Er_2O_3/SiO_2$ double-layer gate dielectric shows low gate leakage current and high capacitance. In this paper, we apply $Er_2O_3/SiO_2$ double-layer gate dielectric as a charge trap layer for the first time. $Er_2O_3/SiO_2$ double-layer thickness is optimized by EDISON Nanophysics simulation tools. Using the simulation results, we fabricated Schottky-barrier silicide source/drain transistor, which has10 um/10um gate length and width, respectively. The nonvolatile device demonstrated very promising characterstics with P/E voltage of 11 V/-11 V, P/E speed of 50 ms/500 ms, data retention of ten years, and endurance of $10^4$ P/E cycles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.5
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• pp.386-389
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• 2009

The electrical characteristics and annealing effects of tunneling dielectrics stacked with $SiO_2$ and $Si_{3}N_{4}$ were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_{3}N_{4}/SiO_2/Si_{3}N_{4}$ (NON), $SiO_2/Si_{3}N_{4}/SiO_2$ (ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS (metal-oxide-semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field. Furthermore, the increased tunneling current through engineered tunneling barriers related to high speed operation can be achieved by annealing processes.

• Structural Engineering and Mechanics
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• v.81 no.6
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• pp.691-703
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• 2022

To obtain the seismic response of lead-cored rubber, shape memory alloy (SMA)-rubber isolation Plate-shell Integrated Concrete Liquid-Storage Structure (PSICLSS), based on a PSICLSS in a water treatment plant, built a scale experimental model, and a shaking table test was conducted. Discussed the seismic responses of rubber isolation, SMA-rubber isolation PSICLSS. Combined with numerical model analysis, the vibration characteristics of rubber isolation PSICLSS are studied. The results showed that the acceleration, liquid sloshing height, hydrodynamic pressure of rubber and SMA-rubber isolation PSICLSS are amplified when the frequency of seismic excitation is close to the main frequency of the isolation PSICLSS. The earthquake causes a significant leakage of liquid, at the same time, the external liquid sloshing height is significantly higher than internal liquid sloshing height. Numerical analysis showed that the low-frequency acceleration excitation causes a more significant dynamic response of PSICLSS. The sinusoidal excitation with first-order sloshing frequency of internal liquid causes a more significant sloshing height of the internal liquid, but has little effect on the structural principal stresses. The sinusoidal excitation with first-order sloshing frequency of external liquid causes the most enormous structural principal stress, and a more significant external liquid sloshing height. In particular, the principal stress of PSICLSSS with long isolation period will be significantly enlarged. Therefore, the stiffness of the isolation layer should be properly adjusted in the design of rubber and SMA-rubber isolation PSICLSS.