• 한국컴퓨터정보학회논문지
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• 제12권4호
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• pp.61-68
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• 2007

모니터 화면상에서 광각으로 멀리보이는 이미지에 대한 기억왜곡현상을 고찰하기 위해 피실험자 170명을 대상으로 두 개의 실험이 실시되었다. 기억 파지기간을 세 가지(즉시, 1시간, 24시간)로 나누고, 시각기억에 대한 재생실험과 재인실험을 실시하였다. 재생실험 결과, 파지기간에 상관없이 피실험자들은 원본이미지보다 전경과 배경을 더 크게 확대 하여 표현하였다. 재인실험결과 파지기간이 1시간과 48시간인 경우에 피실험자들은 원본과 동일한 이미지에 대해 더 광각으로 멀리 촬영된 것으로 인식하였다. 이 결과들은 광각이미지의 시각적 기억, 회상에 경계축소현상이 나타난다는 것을 확인시켜주며, 기존 연구들의 주장과는 달리 경계확장이 일관성 있으며 단방향적으로만 일어나는 현상이 아니라는 것을 보여준다. 또한 연구결과는 경계축소현상을 기억스키마 가설로 설명하는 것이 타당함을 보여준다.

• 대한임베디드공학회논문지
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• 제8권5호
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• pp.235-242
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• 2013

Recently, the number of automotive electrical and electronic system has been increased because the requirements for the convenience and safety of the drivers and passengers are raised. In most cases, the data for controlling the various sensors and automotive electrical and electronic system used in runtime should be stored on the internal or external non-volatile memory of the ECU(Electronic Control Units). However, the non-volatile memory has a constraint with write limitation due to the hardware characteristics. The limitation causes fatal accidents or unexpected results if the non-volatile memory is not managed. In this paper, we propose a management scheme for using non-volatile memory to prolong the writing times based on AUTOSAR(AUTOmotive Open System Architecture) platform. Our proposal is implemented on the CDD(Complex Device Driver) and uses an algorithm which swaps a frequently modified block for a least modified block. Through the development of the prototype, the proposed scheme extends the lifetime of non-volatile memory about 1.08 to 2.48 times than simply using the AUTOSAR standard.

• International Journal of Contents
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• 제5권2호
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• 한국컴퓨터정보학회논문지
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• 제23권4호
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• pp.1-8
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• 2018

In this paper, we propose an adaptive partition cache replacement policy and evaluate the performance of our scheme using various monitoring ratios to help lifetime extension of non-volatile main memory systems without performance degradation. The proposal combines conventional LRU (Least Recently Used) replacement policy and Early Eviction Zone (E2Z), which considers a dirty bit as well as LRU bits to select a candidate block. In particular, this paper shows the performance of non-volatile memory using various monitoring ratios and determines optimized monitoring ratio and partition size of E2Z for reducing the number of writebacks using cache hit counter logic and hit predictor. In the experiment evaluation, we showed that 1:128 combination provided the best results of writebacks and runtime, in terms of performance and complexity trade-off relation, and our proposal yielded up to 42% reduction of writebacks, compared with others.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.514-523
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• 2017

In this paper, we propose Adaptive Writeback-aware Cache management (AWC) to prolong the lifetime of non-volatile main memory systems by reducing the number of writebacks. The last-level cache in AWC is partitioned into Least Recently Used (LRU) segment and LRU using Dirty block Precedence (DP-LRU) segment. The DP-LRU segment evicts clean blocks first for giving reuse opportunity to dirty blocks. AWC can also determine the efficient size of DP-LRU segment for reducing the number of writebacks according to memory access patterns of programs. In the performance evaluation, we showed that AWC reduced the number of writebacks up to 29% and 46%, and saved the energy of a main memory system up to 23% and 49% in a single-core and multi-core, respectively. AWC also reduced the runtime by 1.5% and 3.2% on average compared to previous cache managements for non-volatile main memory systems, in a single-core and a multi-core, respectively.

• 한국정보과학회논문지:시스템및이론
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• 제32권9호
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• pp.457-464
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• 2005

본 논문에서는 임의의 좌표를 기준으로 17가지 접근방식을 지원하는 3차원 메모리 시스템을 제안한다. 제안하는 메모리 시스템은 메모리 모듈 할당 함수와 주소 할당 함수를 토대로 선 접근방식 13가지, 사각형 접근방식 3가지, 육면체 접근방식 1가지 등 모두 17가지 접근방식을 제공한다. 즉, 임의의 좌표에서 임의의 간격을 갖고 17가지 접근방식 중 어떠한 접근방식 내에서도 다수개의 데이타에 동시접근하는 기능을 제공한다. 이를 위해 제안하는 메모리 시스템은 메모리 모듈 선택 회로, 읽기/쓰기를 위한 데이타 라우팅 회로, 주소 계산 및 라우팅 회로들로 구성된다. 본 논문에서 제안하는 메모리 시스템은 응용 프로그램에 따라 쉽게 확장될 수 있으며, 메모리 시스템에 저장된 데이타를 개발자와 프로그래머가 논리적인 3차원 배열로 간주하여 처리할 수 있도록 데이타의 하드웨어 독립성을 지원한다 또한 제안한 메모리 시스템은 다양한 접근방식 내의 다수개의 데이타에 동시접근 할 수 있기 때문에 볼륨 렌더링이나 볼륨 클리핑 등과 같은 다양한 3차원 응용 분야 및 다중해상도를 지원하는 프레임 버퍼를 위한 시스템 구조의 메모리 시스템으로써 적합하다.

• 디지털산업정보학회논문지
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• 제11권4호
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• pp.1-12
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• 2015

This research analyzes the current state of the semiconductor industry delivering the prediction for the future development of the semiconductor industry along with some semiconductor memory's responsive strategies. In the 2014, top 10 semiconductor companies were targeted and studied its growth based on its profitability and growth indications in perspective during three years. The system semiconductor industry with the increase in Hyper-scale customers, proactive actions in the technology consortium, is polarizing caused by increased R&D expense to ensure process scaling limits and high performance, and some results have shown: PC and Mobile slowdown and growth recession phenomenon due to IoT's unclear direction. The leading company is to secure new growth engines through 'Acquiring'. While as the subordinated companies following this consecutive survival through the 'Acquired', the future of system semiconductor industry is to strengthen the market dominance and its techniques by concentrating on the reorganization of the market by few large companies. Accordingly, the semiconductor memory industry is expected to reach the limit of its expansion to domain of system semiconductor, and it is highly suggesting the need of the 'Memory Life Extension' growth strategy.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제11권1호
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• pp.25-32
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• 2011

In this paper, we study the existence and uniqueness of solutions for the impulsive semilinear fuzzy integrodifferential equations with nonlocal conditions and forcing term with memory in n-dimensional fuzzy vector space ($E^n_N$, $d_{\varepsilon}$) by using Banach fixed point theorem. That is an extension of the result of Kwun et al. [9] to impulsive system.

• Coupled systems mechanics
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• 제5권4호
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• pp.329-340
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• 2016

The trigonal shape memory alloys (SMAs) have a great potential to be utilized as the applications with special purposes, such as actuators with high operation frequency. Most studies on the trigonal microstructures typically focus on the well-known classic herringbone pattern, but many other patterns are also possible, such as non-classic herringbone, toothbrush and checkerboard patterns. In the current work, a systematic procedure is developed to find all possible laminate twin microstructures by using geometrically linear compatibility theory. The procedure is verified by SEM images with the information of crystallographic axes of unitcells obtained by EBSD, showing good agreement. Many interesting trigonal R-phase patterns are found in the specimen. Then, their incompatibility are analyzed with nonlinear compatibility theory. The relationship between such incompatibility and the likelihood of occurrence of the microstructures is revealed. The current procedure is rapid, computationally efficient and sufficiently general to allow further extension to other crystal systems and materials.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2024년도 춘계학술발표대회
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• pp.279-282
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• 2024

The Use-after-free (UAF) bug is a long-standing temporal memory safety issue. To prevent UAF attacks, two commonly used approaches are lock-and-key and pointer nullification. Recently, ARM architecture supports the Memory Tagging Extension (MTE) that implemented a lock-and-key mechanism using a 4-bit tag during memory access. Previous research proposed a virtual address tagging scheme utilizing MTE to prevent UAF attacks. In this paper, we aimed to measure a simplified version of the previously proposed virtual address tagging scheme on real machines supporting MTE by implementing a simple module and conducting experiments.