• Proceedings of the Korean Vacuum Society Conference
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• 2007.02a
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• pp.149-149
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• 2007

• Journal of the Korean Society of Safety
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• v.12 no.3
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• pp.60-66
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• 1997

In this paper, a moving object surveillance system, which can extract moving object in real-time, using image subtraction method is described. This technique based on the novelty filter having the structure of neural network associative memory. Digital arithmetic and timing control parts were composed of hardwired controller to treat two-dimensional massive image information. SRAMS having 20 ns access time were used for the image buffer that has high speed write/read property. Image extraction algorithm is discussed and supported by simulation and experiments.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1094-1096
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• 1987

Zero-crossing analysis techniques have been applied to speech recognition. Zero-crossing rate, level-crossing rate and differentiated zero-crossing rate in time domain we used in analyzing speech signals. Speech samples could be stored in memory buffer in real time.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• Journal of Biomedical Engineering Research
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• v.28 no.6
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• pp.803-810
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• 2007

Although synthetic aperture focusing techniques can improve the spatial resolution of ultrasound imaging, they have not been employed in a commercial product because they require a real-time N-channel beamformer with a tremendously increased hardware complexity for simultaneous beamforming along M multiple lines. In this paper, a hardware-efficient beamformer architecture for synthetic aperture focusing is presented. In contrast to the straightforward design using NM delay calculators, the proposed method utilizes only M delay calculators by sharing the same values among the focusing delays which should be calculated at the same time between the N channels for all imaging points along the M scan lines. In general, synthetic aperture beamforming requires M 2-port memories. In the proposed beamformer, the input data for each channel is first upsampled with a 4-fold interpolator and each polyphase component of the interpolator output is stored into a 2-port memory separately, requiring 4M 2-port memories for each channel. By properly limiting the area formed with the synthetic aperture focusing, the input memory buffer can be implemented with only 4 2-port memories and one short multi-port memory.

• International Journal of Internet, Broadcasting and Communication
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• v.8 no.3
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• pp.12-24
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• 2016

Recently, as the price per bit is decreasing at a fast rate, flash memory is considered to be used as primary storage of large-scale database systems. Although flash memory shows off its high speeds of page reads, however, it has a problem of noticeable performance degradation in the presence of increasing update workloads. When updates are requested for pages with random page IDs, in particular, the shortcoming of flash tends to impair significantly the overall performance of a flash-based database system. Therefore, it is important to have a way to efficiently update the B+-tree, when it is stored in flash storage. This is because most of updates in the B+-tree arise at leaf nodes, whose page IDs are in random. In this light, we propose a new flash B+-tree that stores up-to-date versions of leaf nodes in sibling-leaf blocks (SLBs), while updating them. The use of SLBs improves the update performance of B-trees and provides the mechanism for fast key range searches. To verify the performance advantages of the proposed flash B+-tree, we developed a mathematical performance evaluation model that is suited for assessing B-tree operations. The performance comparisons from it show that the proposed flash B+-tree provides faster range searches and reduces more than 50% of update costs.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.5
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• pp.3121-3131
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• 2014

Vulnerabilities related to memory have been known as major threats to the security of a computer system. Actually, the number of attacks using memory vulnerability has been increased. Accordingly, various memory protection mechanisms have been studied and implemented on operating system while new attack techniques bypassing the protection systems have been developed. Especially, buffer overflow attacks have been developed as Return-Oriented Programing(ROP) and Jump-Oriented Programming(JOP) called Code Re-used attack to bypass the memory protection mechanism. Thus, in this paper, I analyzed code re-use attack techniques emerged recently among attacks related to memory, as well as analyzed various detection mechanisms proposed previously. Based on the results of the analyses, a mechanism that could detect various code re-use attacks on a binary level was proposed. In addition, it was verified through experiments that the proposed mechanism could detect code re-use attacks effectively.

• Journal of Advanced Navigation Technology
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• v.20 no.1
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• pp.79-85
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• 2016

Network traffic is increased rapidly, due to mobile and social network, such as smartphones and facebook, in recent web environment. In this paper, we improved web response time of existing system using direct buffer of NIO and DMA. This solved the disadvantage of JAVA, such as CPU performance reduction due to the blocking of I/O, garbage collection of buffer. Key values circulated many data due to priority change put on a hash map operated easily and apply a priority modification algorithm. Large response data is separated and stored at a fast direct buffer and improved performance. This paper showed that the proposed method using NIO was much improved performance, in many test situations of cache hit and cache miss.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.66-76
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• 1998

In this paper, we implement a buffer capable of handling short loops references to statistically lower the miss rate of variable-length instructions stored in the instruction buffer. MAU(Mark Appending Unit) takes the instructions as they are fetched from external memory, performs some initial decode operations and stores the results of the decode in the buffer for reducing multiple decodes when instructions are executed repeatedly such as in a loop. It includes a decision block of whether hit or not for effectively processing branch instructions Each module of the proposed architecture of processing variable-length instruction is described in VHDL structurally and behaviorally and whether it is working well or not is checked on V-System simulator of Model Technology Inc. We synthesized and simulated the architecture using an ASIC Synthesizer tool with 0.6$\mu\textrm{m}$ 5-Volt CMOS COMPASS library. Operation speed is up to 140MHz. The architecture includes about 17,000 gates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.469-472
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• 1999

CeO$_2$ thin films have used in wide applications such as SOI, buffer layer, antirflection coating, and gate dielectric layer. CeO$_2$takes one of the cubic system of fluorite structure and shows similar lattice constant (a=0.541nm) to silicon (a=0.543nm). We investigated CeO$_2$films as buffer layer material for nonvolatile memory device application of a single transistor. Aiming at the single transistor FRAM device with a gate region configuration of PZT/CeO$_2$ /P-Si , this paper focused on CeO$_2$-Si interface properties. CeO$_2$ films were grown on P-type Si(100) substrates by 13.56MHz RF magnetron sputtering system using a 2 inch Ce metal target. To characterize the CeO$_2$ films, we employed an XRD, AFM, C-V, and I-V for structural, surface morphological, and electrical property investigations, respectively. This paper demonstrates the best lattice mismatch as low as 0.2 % and average surface roughness down to 6.8 $\AA$. MIS structure of CeO$_2$ shows that breakdown electric field of 1.2 MV/cm, dielectric constant around 13.6 at growth temperature of 200 $^{\circ}C$, and interface state densities as low as 1.84$\times$10$^{11}$ cm $^{-1}$ eV$^{-1}$ . We probes the material properties of CeO$_2$ films for a buffer layer of FRAM applications.